Cortex-A15 MPCore Technical Reference Manual: 8.3.1. Distributor register summary

8.3.1. Distributor register summary

The Distributor centralizes all interrupt sources, determines the priority of each interrupt, and for each CPU interface dispatches the interrupt with the highest priority to the interface for priority masking and preemption handling.

The Distributor provides a programming interface for:

globally enabling the forwarding of interrupts to the CPU interfaces
enabling or disabling each interrupt
setting the priority level of each interrupt
routing each interrupt to its target processor
setting each shared peripheral interrupt to be level-sensitive or edge-triggered
setting each interrupt as either Group 0 or Group 1, see the ARM Generic Interrupt Controller (GIC) Architecture Specification for information on interrupt grouping
forwarding an SGI to one or more target processors
visibility of the state of each interrupt
a mechanism for software to set or clear the pending state of a peripheral interrupt.

In addition, the Distributor provides:

visibility of the state of each interrupt
a mechanism for software to set or clear the pending state of a peripheral interrupt.

The Distributor provides the ability to set interrupts as either:

Secure Group 0
Non-secure Group 1
Secure Group 1.

See the ARM Generic Interrupt Controller (GIC) Architecture Specification for information on interrupt grouping.

Table 8.3 shows the register map for the Distributor. The offsets in this table are relative to the Distributor block base address as shown in Table 8.1.

The GICD_IPR and GICD_IPTR registers are byte-accessible and word-accessible. All other registers in Table 8.3 are word-accessible. Registers not described in Table 8.3 are RAZ/WI.

Table 8.3. Distributor register summary

Offset	Name	Type	Reset	Description
`0x000`	GICD_CTLR	RW^[a]	`0x00000000`	Distributor Control Register, see ARM Generic Interrupt Controller Architecture Specification
`0x004`	GICD_TYPER	RO	Configuration dependent	Interrupt Controller Type Register
`0x008`	GICD_IIDR	RO	`0x0000043B`	Distributor Implementer Identification Register
`0x080 - 0x09C`	GICD_IGROUPRn	RW^[b]	`0x00000000`	Interrupt Group Registers, see ARM Generic Interrupt Controller Architecture Specification
`0x100`	GICD_ISENABLERn	RW	`0x0000FFFF`^[c]	Interrupt Set-Enable Registers, see ARM Generic Interrupt Controller Architecture Specification
`0x104 - 0x11C`	GICD_ISENABLERn	RW	`0x00000000`
`0x180`	GICD_ICENABLERn	RW	`0x0000FFFF`^[c]	Interrupt Clear-Enable Registers, see ARM Generic Interrupt Controller Architecture Specification
`0x184 - 0x19`C	GICD_ICENABLERn	RW	`0x00000000`
`0x200 - 0x21C`	GICD_ISPENDRn	RW	`0x00000000`	Interrupt Set-Pending Registers, see ARM Generic Interrupt Controller Architecture Specification
`0x280 - 0x29C`	GICD_ICPENDRn	RW	`0x00000000`	Interrupt Clear-Pending Registers, see ARM Generic Interrupt Controller Architecture Specification
`0x300 - 0x31C`	GICD_ISACTIVERn	RW	`0x00000000`	Interrupt Set-Active Registers, see ARM Generic Interrupt Controller Architecture Specification
`0x380 - 0x39C`	GICD_ICACTIVERn	RW	`0x00000000`	Interrupt Clear-Active Registers, see ARM Generic Interrupt Controller Architecture Specification
`0x400 - 0x4FC`	GICD_IPRIORITYRn	RW	`0x00000000`	Interrupt Priority Registers, see ARM Generic Interrupt Controller Architecture Specification
`0x800 - 0x81C`	GICD_ITARGETSRn	RO^[d]	Configuration dependent	Interrupt Processor Targets Registers, see ARM Generic Interrupt Controller Architecture Specification
`0x820 - 0x8FC`	GICD_ITARGETSRn	RW^[d]	`0x00000000`
`0xC00`	GICD_ICFGRn	RO	`0xAAAAAAAA`^[e]	Interrupt Configuration Register
`0xC04`		RO	`0x55540000`^[e]
`0xC08 - 0xC3C`		RW	`0x55555555`^[e]
`0xD00`	GICD_PPISR	RO	`0x00000000`	Private Peripheral Interrupt Status Register
`0xD04 -0xD1C`	GICD_SPISRn	RO	`0x00000000`	Shared Peripheral Interrupt Status Registers
`0xF00`	GICD_SGIR	WO	-	Software Generated Interrupt Register, see ARM Generic Interrupt Controller Architecture Specification
`0xF10 - 0xF1C`	GICD_CPENDSGIRn	RW	`0x00000000`	SGI Clear-Pending Registers, see ARM Generic Interrupt Controller Architecture Specification
`0xF20 - 0xF2C`	GICD_SPENDSGIRn	RW	`0x00000000`	SGI Set-Pending Registers, see ARM Generic Interrupt Controller Architecture Specification
`0xFD0`	GICD_PIDR4	RO	`0x04`	Peripheral ID4 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFD4`	GICD_PIDR5	RO	`0x00`	Peripheral ID5 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFD8`	GICD_PIDR6	RO	`0x00`	Peripheral ID6 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFDC`	GICD_PIDR7	RO	`0x00`	Peripheral ID7 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFE0`	GICD_PIDR0	RO	`0x90`	Peripheral ID0 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFE4`	GICD_PIDR1	RO	`0xB4`	Peripheral ID1 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFE8`	GICD_PIDR2	RO	`0x2B`	Peripheral ID2 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFEC`	GICD_PIDR3	RO	`0x00`	Peripheral ID3 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFF0`	GICD_CIDR0	RO	`0x0D`	Component ID0 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFF4`	GICD_CIDR1	RO	`0xF0`	Component ID1 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFF8`	GICD_CIDR2	RO	`0x05`	Component ID2 Register, see ARM Generic Interrupt Controller Architecture Specification
`0xFFC`	GICD_CIDR3	RO	`0xB1`	Component ID3 Register, see ARM Generic Interrupt Controller Architecture Specification
^[a]You cannot modify the secure copy of this register if CFGSDISABLE is asserted. ^[b]This register is only accessible with a Secure access. ^[c]The reset value for the register that contains the SGI and PPI interrupts is `0x0000FFFF` because SGIs are always enabled. ^[d]The register that contains the SGI and PPI interrupts is read-only and the reset value is configuration-dependent. For Cortex-A15 configurations with only one processor, these registers are RAZ/WI. ^[e]The reset value for the register that contains the SGI interrupts is `0xAAAAAAAA`. The reset value for the register that contains the PPI interrupts is `0x55540000`. The reset value for the registers that contain the SPI interrupts is `0x55555555`.

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