Cortex-A15 MPCore Technical Reference Manual: 4.3.11. Memory Model Feature Register 0

The ID_MMFR0 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support.

Usage constraints

The ID_MMFR0 is:

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.9 shows the ID_MMFR0 bit assignments.

Figure 4.9. ID_MMFR0 bit assignments

Table 4.37 shows the ID_MMFR0 bit assignments.

Table 4.37. ID_MMFR0 bit assignments

Bits	Name	Function
[31:28]	Innermost shareability	Indicates the innermost shareability domain implemented: `0x1` Processor implements hardware coherency support.
[27:24]	FCSE	Indicates support for Fast Context Switch Extension (FCSE): `0x0` Processor does not support FCSE.
[23:20]	Auxiliary registers	Indicates support for Auxiliary registers: `0x2` Processor supports the ACTLR and ADFSR. See Auxiliary Control Register and Auxiliary Data Fault Status Register.
[19:16]	TCM	Indicates support for TCMs and associated DMAs: `0x0` Processor does not support TCM.
[15:12]	Shareability levels	Indicates the number of shareability levels implemented: `0x1` Processor implements two levels of shareability.
[11:8]	Outermost shareability	Indicates the outermost shareability domain implemented: `0x1` Processor supports hardware coherency.
[7:4]	PMSA	Indicates support for a Protected Memory System Architecture (PMSA): `0x0` Processor does not support PMSA.
[3:0]	VMSA	Indicates support for a Virtual Memory System Architecture (VMSA). `0x5` Processor supports: VMSAv7, with support for remapping and the Access flag Privileged Execute Never (PXN) bit in the Short-descriptor translation table format Privileged Execute Never (PXN) bit in the Long-descriptor translation table format.

To access the ID_MMFR0, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 4; Read Memory Model Feature Register 0

Copyright © 2011-2012 ARM. All rights reserved.	ARM DDI 0438E
Non-Confidential	ID040512
PDF version