Cortex-A15 MPCore Technical Reference Manual: 4.3.30. Secure Configuration Register

4.3.30. Secure Configuration Register

The SCR characteristics are:

Purpose

Defines the configuration of the current security state. It specifies:

the security state of the processor, Secure or Non-secure
what mode the processor branches to, if an IRQ, FIQ or external abort occurs
whether the CPSR.F and CPSR.A bits can be modified when SCR.NS is 1.

Usage constraints

The SCR is:

a read/write register
a Restricted access register that exists only in the Secure state
only accessible in Secure PL1 modes.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.26 shows the SCR bit assignments.

Figure 4.26. SCR bit assignments

Table 4.55 shows the SCR bit assignments.

Table 4.55. SCR bit assignments

Bits	Name	Function
[31:10]	-	Reserved, UNK/SBZP.
[9]	SIF	Secure Instruction Fetch. When the processor is in Secure state, this bit disables instruction fetches from Non-secure memory: 0 Secure state instruction fetches from Non-secure memory are permitted. This is the reset value. 1 Secure state instruction fetches from Non-secure memory are not permitted.
[8]	HCE	Hyp Call enable. This bit enables the use of `HVC` instruction from Non-secure PL1 modes: 0 The `HVC` instruction is undefined in Non-secure PL1 modes, and unpredictable in Hyp mode. This is the reset value. 1 The `HVC` instruction is enabled in Non-secure PL1 modes, and performs a Hyp Call.
[7]	SCD	Secure Monitor Call disable. This bit causes the `SMC` instruction to be undefined in Non-secure state: 0 The `SMC` instruction executes normally in Non-secure state, and performs a Secure Monitor Call. This is the reset value. 1 The `SMC` instruction is undefined in Non-secure state. A trap of the `SMC` instruction to Hyp mode takes priority over the value of this bit. See the ARM Architecture Reference Manual for more information.
[6]	nET	Not Early Termination. This bit disables early termination of data operations. This bit is not implemented, UNK/SBZP.
[5]	AW	A bit writable. This bit controls whether CPSR.A can be modified in Non-secure state. For the Cortex-A15 MPCore processor: This bit has no effect on whether CPSR.A can be modified in Non-secure state. The AW bit can be modified in either security state. This bit, with the HCR.AMO bit, determines whether CPSR.A has any effect on exceptions that are routed to a Non-secure mode.
[4]	FW	F bit writable. This bit controls whether CPSR.F can be modified in Non-secure state. For the Cortex-A15 MPCore processor: This bit has no effect on whether CPSR.F can be modified in Non-secure state. The FW bit can be modified in either security state. This bit, with the HCR.FMO bit, determines whether CPSR.F has any effect on exceptions that are routed to a Non-secure mode.
[3]	EA	External Abort handler. This bit controls which mode takes external aborts: 0 External aborts taken in Abort mode. This is the reset value. 1 External aborts taken in Monitor mode.
[2]	FIQ	FIQ handler. This bit controls which mode takes FIQ exceptions: 0 FIQs taken in FIQ mode. This is the reset value. 1 FIQs taken in Monitor mode.
[1]	IRQ	IRQ handler. This bit controls which mode takes IRQ exceptions: 0 IRQs taken in IRQ mode. This is the reset value. 1 IRQs taken in Monitor mode.
[0]	NS	Non Secure bit. Except when the processor is in Monitor mode, this bit determines the security state of the processor: 0 Secure. This is the reset value. 1 Non-secure. Note When the processor is in Monitor mode, it is always in Secure state, regardless of the value of the NS bit. The value of the NS bit also affects the accessibility of the Banked CP15 registers in Monitor mode. See the ARM Architecture Reference Manual for more information on the NS bit.

To access the SCR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c1, 0; Read Secure Configuration Register data

MCR p15, 0, <Rt>, c1, c1, 0; Write Secure Configuration Register data

Copyright © 2011-2012 ARM. All rights reserved.	ARM DDI 0438E
Non-Confidential	ID040512
PDF version

4.3.30. Secure Configuration Register

Note