| Copyright © 2011-2012 ARM. All rights reserved. | ARM DDI 0438E |
| Non-Confidential | ID040512 |
 PDF version | |
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Accelerator Coherency Port (ACP) is implemented as an AXI3 slave interface that supports the following features:
configurable 64-bit or 128-bit read and write interfaces
all burst types such as INCR, WRAP, or FIXED.
ACP does not support fixed addressing mode to Normal Memory.
The Cortex-A15 MPCore processor does not support a 64-bit ACE with a 128-bit ACP.
This section describes ACP in:
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DDI 0438E |
| Non-Confidential | ID040512 |
| PDF version | |
| Home > Level 2 Memory System > ACP |