Cortex-A15 MPCore Technical Reference Manual: 4.3.27. System Control Register

4.3.27. System Control Register

The SCTLR characteristics are:

Purpose

Provides the top level control of the system, including its memory system.

Usage constraints

The SCTLR:

Is a read/write register.
Banked for Secure and Non-secure states for all implemented bits.
Is only accessible from PL1 or higher.
Has write access to the Secure copy of the register disabled when the CP15SDISABLE signal is asserted HIGH. Attempts to write to this register in Secure PL1 modes when CP15SDISABLE is HIGH result in an Undefined Instruction exception.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.23 shows the SCTLR bit assignments.

Figure 4.23. SCTLR bit assignments

Table 4.52 shows the SCTLR bit assignments.

Table 4.52. SCTLR bit assignments

Bits	Name	Access	Function
[31]	-	-	Reserved, UNK/SBZP.
[30]	TE	Banked	Thumb Exception enable. This bit controls whether exceptions are taken in ARM or Thumb state: 0 Exceptions, including reset, taken in ARM state. 1 Exceptions, including reset, taken in Thumb state. The primary input CFGTE defines the reset value of the TE bit.
[29]	AFE	Banked	Access flag enable. This bit enables use of the AP[0] bit in the translation table descriptors as the Access flag. It also restricts access permissions in the translation table descriptors to the simplified model as described in the ARM Architecture Reference Manual: 0 In the translation table descriptors, AP[0] is an access permissions bit. The full range of access permissions is supported. No Access flag is implemented. This is the reset value. 1 In the translation table descriptors, AP[0] is the Access flag. Only the simplified model for access permissions is supported. When TTBCR.EAE is set to 1, to enable use of the Long-descriptor translation table format, this bit is UNK/SBOP.
[28]	TRE	Banked	TEX remap enable. This bit enables remapping of the TEX[2:1] bits for use as two translation table bits that can be managed by the operating system. Enabling this remapping also changes the scheme used to describe the memory region attributes in the VMSA: 0 TEX remap disabled. TEX[2:0] are used, with the C and B bits, to describe the memory region attributes. This is the reset value. 1 TEX remap enabled. TEX[2:1] are reassigned for use as bits managed by the operating system. The TEX[0], C and B bits are used to describe the memory region attributes, with the MMU remap registers. When TTBCR.EAE is set to 1, to enable use of the Long-descriptor translation table format, this bit is UNK/SBOP. See the ARM Architecture Reference Manual for more information.
[27]	-	-	Reserved, RAZ/WI.
[26]	-	-	Reserved, RAZ/SBZP.
[25]	EE	Banked	Exception Endianness. The value of this bit defines the value of the CPSR.E bit on entry to an exception vector, including reset. This value also indicates the endianness of the translation table data for translation table lookups: 0 Little endian. 1 Big endian. The primary input CFGEND defines the reset value of the EE bit.
[24]	-	-	Reserved, RAZ/WI.
[23:22]	-	-	Reserved, RAO/SBOP.
[21]	-	-	Reserved, RAZ/WI.
[20]	UWXN	Banked	Unprivileged write permission implies PL1 Execute Never (XN). This bit can be used to require all memory regions with unprivileged write permissions to be treated as XN for accesses from software executing at PL1: 0 Regions with unprivileged write permission are not forced to be XN. This is the reset value. 1 Regions with unprivileged write permission are forced to be XN for accesses from software executing at PL1. This bit resets to 0 in both the Secure and the Non-secure copy of the register. See the ARM Architecture Reference Manual for more information.
[19]	WXN	Banked	Write permission implies Execute Never (XN). This bit can be used to require all memory regions with write permissions to be treated as XN: 0 Regions with write permission are not forced to be XN. This is the reset value. 1 Regions with write permissions are forced to be XN. This bit resets to 0 in both the Secure and the Non-secure copy of the register. See the ARM Architecture Reference Manual for more information.
[18]	-	-	Reserved, RAO/SBOP.
[17]	-	-	Reserved, RAZ/WI.
[16]	-	-	Reserved, RAO/SBOP.
[15]	-	-	Reserved, RAZ/SBZP.
[14]	-	-	Reserved, RAZ/WI.
[13]	V	Banked	Vectors bit. This bit selects the base address of the exception vectors: 0 Normal exception vectors, base address `0x00000000`. This base address can be remapped by updating the Vector Base Address Register. See the ARM Architecture Reference Manual. 1 High exception vectors, base address `0xFFFF0000`. This base address is never remapped. The primary input VINITHI defines the reset value of the V bit.
[12]	I	Banked	Instruction cache enable. This is a global enable bit for instruction caches: 0 Instruction caches disabled. This is the reset value. 1 Instruction caches enabled.
[11]	Z	Banked	Branch prediction enable. This bit is used to enable branch prediction, also called program flow prediction: 0 Program flow prediction disabled. This is the reset value. 1 Program flow prediction enabled.
[10]	SW	Banked	SWP/SWPB enable bit. This bit enables the use of `SWP` and `SWPB` instructions: 0 `SWP` and `SWPB` are undefined. This is the reset value. 1 `SWP` and `SWPB` perform as described in the ARM Architecture Reference Manual.
[9:7]	-	-	Reserved, RAZ/SBZP.
[6:3]	-	-	Reserved, RAO/SBOP.
[2]	C	Banked	Cache enable. This is a global enable bit for data and unified caches: 0 Data and unified caches disabled. This is the reset value. 1 Data and unified caches enabled. See the ARM Architecture Reference Manual for more information.
[1]	A	Banked	Alignment check enable. This is the enable bit for Alignment fault checking: 0 Alignment fault checking disabled. This is the reset value. 1 Alignment fault checking enabled. See the ARM Architecture Reference Manual for more information.
[0]	M	Banked	MMU enable. This is a global enable bit for the PL1 and PL0 stage 1 MMU: 0 PL1 and PL0 stage 1 MMU disabled. This is the reset value. 1 PL1 and PL0 stage 1 MMU enabled. See the ARM Architecture Reference Manual for more information.

To access the SCTLR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c0, 0 ; Read System Control Register

MCR p15, 0, <Rt>, c1, c0, 0 ; Write System Control Register

Copyright © 2011-2012 ARM. All rights reserved.	ARM DDI 0438E
Non-Confidential	ID040512
PDF version