Cortex-A15 MPCore Technical Reference Manual: A.14.2. MBIST interface

A.14.2. MBIST interface

Table A.33 shows the L1 Memory Built-In Self Test (MBIST) interface signals. The value of N is one less than the number of processors in your design.

Table A.33. L1 MBIST interface signals

Signal	Type	Description
nMBISTRESET1	Input	L1 MBIST reset
MBISTACK1[N:0]	Output	L1 MBIST test acknowledge
MBISTADDR1[12:0]	Input	L1 MBIST logical address
MBISTARRAY1[4:0]	Input	L1 MBIST array selector
MBISTBE1[7:0]	Input	L1 MBIST bit write enable
MBISTCFG1	Input	L1 MBIST configuration
MBISTINDATA1[99:0]	Input	L1 MBIST data in
MBISTOUTDATA1[99:0]	Output	L1 MBIST data out
MBISTREADEN1	Input	L1 MBIST read enable
MBISTREQ1[N:0]	Input	L1 MBIST test request
MBISTWRITEEN1	Input	L1 MBIST write enable

Table A.34 shows the L2 MBIST interface signals.

Table A.34. L2 MBIST interface signals

Signals	Type	Description
nMBISTRESET2	Input	L2 MBIST reset
MBISTACK2	Output	L2 MBIST test acknowledge
MBISTADDR2[15:0]	Input	L2 MBIST logical address
MBISTARRAY2[4:0]	Input	L2 MBIST array selector
MBISTBE2[15:0]	Input	L2 MBIST bit write enable
MBISTCFG2[6:0]	Input	L2 MBIST configuration
MBISTINDATA2[127:0]	Input	L2 MBIST data in
MBISTOUTDATA2[127:0]	Output	L2 MBIST data out
MBISTREADEN2	Input	L2 MBIST read enable
MBISTREQ2	Input	L2 MBIST test request
MBISTWRITEEN2	Input	L2 MBIST write enable

Copyright © 2011-2012 ARM. All rights reserved.	ARM DDI 0438E
Non-Confidential	ID040512
PDF version