Cortex-A15 MPCore Technical Reference Manual: 11.3. PMU register summary

11.3. PMU register summary

The PMU counters and their associated control registers are accessible from the internal CP15 interface and from the Debug APB interface.

Table 11.1 gives a summary of the Cortex-A15 PMU registers.

Table 11.1. PMU register summary

Register number	Offset	CRn	Op1	CRm	Op2	Name	Type	Description
0	`0x000`	c9	0	c13	2	PMXEVCNTR0	RW	Event Count Register, see the ARM Architecture Reference Manual
1	`0x004`	c9	0	c13	2	PMXEVCNTR1	RW
2	`0x008`	c9	0	c13	2	PMXEVCNTR2	RW
3	`0x00C`	c9	0	c13	2	PMXEVCNTR3	RW
4	`0x010`	c9	0	c13	2	PMXEVCNTR4	RW
5	`0x014`	c9	0	c13	2	PMXEVCNTR5	RW
6-30	`0x018-0x78`	-	-	-	-	-	-	Reserved
31	`0x07C`	c9	0	c13	0	PMCCNTR	RW	Cycle Count Register, see the ARM Architecture Reference Manual
32-255	`0x080-0x3FC`	-	-	-	-	-		Reserved
256	`0x400`	c9	0	c13	1	PMXEVTYPER0	RW	Event Type Select Register, see the ARM Architecture Reference Manual
257	`0x404`	c9	0	c13	1	PMXEVTYPER1	RW
258	`0x408`	c9	0	c13	1	PMXEVTYPER2	RW
259	`0x40C`	c9	0	c13	1	PMXEVTYPER3	RW
260	`0x410`	c9	0	c13	1	PMXEVTYPER4	RW
261	`0x414`	c9	0	c13	1	PMXEVTYPER5	RW
262-286	`0x418-0x478`	-	-	-	-	-	-	Reserved
287	`0x47C`	c9	0	c13	1	PMXEVTYPER31	RW	Performance Monitors Event Type Select Register 31, see the ARM Architecture Reference Manual
288-767	`0x480-0xBFC`	-	-	-	-	-	-	Reserved
768	`0xC00`	c9	0	c12	1	PMCNTENSET	RW	Count Enable Set Register, see the ARM Architecture Reference Manual
769-775	`0xC04-0xC1C`	-	-	-	-	-	-	Reserved
776	`0xC20`	c9	0	c12	2	PMCNTENCLR	RW	Count Enable Clear Register, see the ARM Architecture Reference Manual
777-783	`0xC24-0xC3C`	-	-	-	-	-	-	Reserved
784	`0xC40`	c9	0	c14	1	PMINTENSET	RW	Interrupt Enable Set Register, see the ARM Architecture Reference Manual
785-791	`0xC44-0xC5C`	-	-	-	-	-	-	Reserved
792	`0xC60`	c9	0	c14	2	PMINTENCLR	RW	Interrupt Enable Clear Register, see the ARM Architecture Reference Manual
793-799	`0xC64-0xC7C`	-	-	-	-	-	-	Reserved
800	`0xC80`	c9	0	c12	3	PMOVSR	RW	Overflow Flag Status Register, see the ARM Architecture Reference Manual
801-807	`0xC84-0xC9C`	-	-	-	-	-	-	Reserved
808	`0xCA0`	c9	0	c12	4	PMSWINC	WO	Software Increment Register, see the ARM Architecture Reference Manual
809-815	`0xCA4-0xCBC`	-	-	-	-	-	-	Reserved
816	`0xCC0`	c9	0	c14	3	PMOVSSET	RW	Performance Monitor Overflow Status Set Register, see the ARM Architecture Reference Manual
817-895	`0xCC4-0xDFC`	-	-	-	-	-	-	Reserved
896	`0xE00`	-	-	-	-	PMCFGR	RO	Performance Monitor Configuration Register
897	`0xE04`	c9	0	c12	0	PMCR	RW	Performance Monitor Control Register
898	`0xE08`	c9	0	c14	0	PMUSERENR	RW	User Enable Register, see the ARM Architecture Reference Manual
899-903	`0xE0C-0xE1C`	-	-	-	-	-	-	Reserved
904	`0xE20`	c9	0	c12	6	PMCEID0	RO	Table 11.4
905	`0xE24`	c9	0	c12	7	PMCEID1	RO	Performance Monitor Common Event Identification Register 1
906-1003	`0xE28-0xFAC`	-	-	-	-	-	-	Reserved
1004	`0xFB0`	-	-	-	-	PMLAR	WO	Lock Access Register, see the ARM Architecture Reference Manual
1005	`0xFB4`	-	-	-	-	PMLSR	RO	Lock Status Register, see the ARM Architecture Reference Manual
1006	`0xFB8`					PMAUTHSTATUS	RO	Authentication Status Register, see the ARM Architecture Reference Manual
1007-1010	`0xFBC-0xFC8`	-	-	-	-	-	-	Reserved
1011	`0xFCC`	-	-	-	-	PMDEVTYPE	RO	Device Type Register, see the ARM Architecture Reference Manual
1012	`0xFD0`	-	-	-	-	PMPID4	RO	Peripheral Identification Registers
1013	`0xFD4`	-	-	-	-	PMPID5	RO
1014	`0xFD8`	-	-	-	-	PMPID6	RO
1015	`0xFDC`	-	-	-	-	PMPID7	RO
1016	`0xFE0`	-	-	-	-	PMPID0	RO
1017	`0xFE4`	-	-	-	-	PMPID1	RO
1018	`0xFE8`	-	-	-	-	PMPID2	RO
1019	`0xFEC`	-	-	-	-	PMPID3	RO
1020	`0xFF0`	-	-	-	-	PMCID0	RO	Component Identification Registers
1021	`0xFF4`	-	-	-	-	PMCID1	RO
1022	`0xFF8`	-	-	-	-	PMCID2	RO
1023	`0xFFC`	-	-	-	-	PMCID3	RO
-	-	c9	0	c12	5	PMSELR	RW	Event Counter Selection Register, see the ARM Architecture Reference Manual

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