full implementation of the ARMv7-A architecture instruction set with the architecture extensions listed in Compliance

superscalar, variable-length, out-of-order pipeline

dynamic branch prediction with Branch Target Buffer (BTB) and Global History Buffer (GHB), a return stack, and an indirect predictor

three separate 32-entry fully-associative Level 1 (L1) Translation Look-aside Buffers (TLBs), one for instruction, one for data loads, and one for data stores

4-way set-associative 512-entry Level 2 (L2) TLB in each processor

fixed 32KB L1 instruction and data caches

shared L2 cache of 512KB, 1MB, 2MB, or 4MB configurable size

optional Error Correction Code (ECC) protection for L1 data cache and L2 cache, and parity protection for L1 instruction cache

AMBA 4 AXI Coherency Extensions (ACE) master interface

Accelerator Coherency Port (ACP) that is implemented as an AXI3 slave interface

Program Trace Macrocell (PTM) based on the CoreSight Program Flow Trace (PFT) v1.1 architecture

Performance Monitor Unit (PMU) based on PMUv2 architecture

cross trigger interfaces for multi-processor debugging

VFP component only or optionally implemented VFP and NEON components

optional Generic Interrupt Controller (GIC) that supports up to 224 Shared Peripheral Interrupts (SPIs)

ARM generic 64-bit timers for each processor

support for power management with multiple power domains.