The L2 memory system has two outputs that indicate asynchronous error conditions. An asynchronous external error condition exists when either:

If an asynchronous error condition is detected, the corresponding bit in the L2 Extended Control Register is asserted. The asynchronous error condition can be cleared by writing 1'b0 to the corresponding bit of the L2ECTLR. Software can only clear the L2ECTLR. Any attempt to assert the error by writing the L2ECTLR is ignored. See L2 Extended Control Register for more information.

Any external error associated with a load instruction is reported back to the requestor along with an error response and this might trigger an abort.