| Copyright © 2011-2012 ARM. All rights reserved. | ARM DDI 0438E |
| Non-Confidential | ID040512 |
 PDF version | |
| Home > Level 2 Memory System > About the L2 memory system |
| |||
| Home > Level 2 Memory System > About the L2 memory system | |||
The L2 memory system consists of a tightly-coupled L2 cache and an integrated Snoop Control Unit (SCU), connecting up to four processors within a Cortex-A15 MPCore device. The L2 memory system also interfaces with an AMBA 4 (ACE) interconnect and an Accelerator Coherency Port (ACP) that is implemented as an AXI3 slave interface.
The features of the L2 memory system include:
configurable L2 cache size of 512KB, 1MB, 2MB and 4MB
fixed line length of 64 bytes
physically indexed and tagged cache
16-way set-associative cache structure
banked pipeline structures
strictly enforced inclusion property with L1 data caches
random cache-replacement policy
configurable 64-bit or 128-bit wide ACE with support for multiple outstanding requests
configurable 64-bit or 128-bit wide ACP with support for multiple incoming requests
duplicate copies of the L1 data cache directories for coherency support
optional Error Correction Code (ECC) support
optional hardware prefetch support
software-programmable variable latency RAMs
register slice support for large L2 cache sizes to minimize impact on routing delays
MBIST support.
The Cortex-A15 MPCore processor does not support TLB or cache lockdown.
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DDI 0438E |
| Non-Confidential | ID040512 |
| PDF version | |
| Home > Level 2 Memory System > About the L2 memory system |