| Copyright © 2011-2012 ARM. All rights reserved. | ARM DDI 0438E |
| Non-Confidential | ID040512 |
 PDF version | |
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The L1 memory system consists of separate instruction and data caches.
The L1 instruction memory system has the following features:
32KB 2-way set-associative instruction cache
fixed line length of 64 bytes
parity protection per 16 bits
instruction cache that is Physically-Indexed and Physically-Tagged (PIPT)
Least Recently Used (LRU) cache replacement policy
MBIST support.
The L1 data memory system has the following features:
32KB 2-way set-associative data cache
fixed line length of 64 bytes
ECC protection per 32 bits
data cache that is PIPT
out-of-order, speculative, nonblocking load requests to Normal memory, Strongly ordered, and Device memory
LRU cache replacement policy
MBIST support.
The Cortex-A15 MPCore processor does not support TLB or cache lockdown.
| Copyright © 2011-2012 ARM. All rights reserved. | ARM DDI 0438E |
| Non-Confidential | ID040512 |
| PDF version | |
| Home > Level 1 Memory System > About the L1 memory system |