Cortex™-A15 MPCore™ Technical Reference Manual

Revision: r3p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-A15 MPCore processor
1.2. Compliance
1.2.1. ARM architecture
1.2.2. Advanced Microcontroller Bus Architecture
1.2.3. Debug architecture
1.2.4. Generic Interrupt Controller architecture
1.2.5. Generic Timer architecture
1.2.6. Program Flow Trace architecture
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation and design flow
1.7.1. Documentation
1.7.2. Design flow
1.8. Product revisions
1.8.1. r0p0 - r0p1
1.8.2. r0p1 - r0p2
1.8.3. r0p2 - r0p3
1.8.4. r0p3 - r1p0
1.8.5. r1p0 - r2p0
1.8.6. r2p0 - r2p1
1.8.7. r2p1 - r2p2
1.8.8. r2p2 - r3p0
1.8.9. r3p0 - r3p1
2. Functional Description
2.1. About the Cortex-A15 MPCore processor functions
2.1.1. Components of the processor
2.2. Interfaces
2.2.1. AXI
2.2.2. APB
2.2.3. ATB
2.2.4. Cross trigger
2.2.5. DFT
2.2.6. MBIST controller
2.3. Clocking and resets
2.3.1. Clocks
2.3.2. Resets
2.4. Power management
2.4.1. Dynamic power management
2.4.2. Power domains
2.4.3. Power modes
2.4.4. Event communication using WFE and SEV instructions
3. Programmers Model
3.1. About the programmers model
3.2. ThumbEE architecture
3.3. Jazelle Extension
3.3.1. Register summary
3.3.2. Register description
3.4. Advanced SIMD and VFP Extensions
3.5. Security Extensions architecture
3.5.1. System boot sequence
3.5.2. Security Extensions configuration write access disable
3.6. Virtualization Extensions architecture
3.7. Large Physical Address Extension architecture
3.8. Multiprocessing Extensions
3.9. Modes of operation and execution
3.9.1. Operating states
3.10. Memory model
4. System Control
4.1. About system control
4.1.1. Registers affected by CP15SDISABLE
4.2. Register summary
4.2.1. c0 registers
4.2.2. c1 registers
4.2.3. c2 registers
4.2.4. c3 registers
4.2.5. c5 registers
4.2.6. c6 registers
4.2.7. c7 registers
4.2.8. c8 registers
4.2.9. c9 registers
4.2.10. c10 registers
4.2.11. c12 registers
4.2.12. c13 registers
4.2.13. c14 registers
4.2.14. c15 registers
4.2.15. 64-bit registers
4.2.16. Identification registers
4.2.17. Virtual memory control registers
4.2.18. PL1 Fault handling registers
4.2.19. Other system control registers
4.2.20. Cache maintenance operations
4.2.21. TLB maintenance operations
4.2.22. Address translation operations
4.2.23. Miscellaneous operations
4.2.24. Performance monitor registers
4.2.25. Security Extensions registers
4.2.26. Virtualization Extensions registers
4.2.27. Hyp mode TLB maintenance operations
4.2.28. Generic Timer registers
4.2.29. Implementation defined registers
4.3. Register descriptions
4.3.1. Main ID Register
4.3.2. Cache Type Register
4.3.3. TCM Type Register
4.3.4. TLB Type Register
4.3.5. Multiprocessor Affinity Register
4.3.6. Revision ID Register
4.3.7. Processor Feature Register 0
4.3.8. Processor Feature Register 1
4.3.9. Debug Feature Register 0
4.3.10. Auxiliary Feature Register 0
4.3.11. Memory Model Feature Register 0
4.3.12. Memory Model Feature Register 1
4.3.13. Memory Model Feature Register 2
4.3.14. Memory Model Feature Register 3
4.3.15. Instruction Set Attribute Register 0
4.3.16. Instruction Set Attribute Register 1
4.3.17. Instruction Set Attribute Register 2
4.3.18. Instruction Set Attribute Register 3
4.3.19. Instruction Set Attribute Register 4
4.3.20. Instruction Set Attribute Register 5
4.3.21. Cache Size ID Register
4.3.22. Cache Level ID Register
4.3.23. Auxiliary ID Register
4.3.24. Cache Size Selection Register
4.3.25. Virtualization Processor ID Register
4.3.26. Virtualization Multiprocessor ID Register
4.3.27. System Control Register
4.3.28. Auxiliary Control Register
4.3.29. Coprocessor Access Control Register
4.3.30. Secure Configuration Register
4.3.31. Non-Secure Access Control Register
4.3.32. Hyp System Control Register
4.3.33. Hyp Auxiliary Control Register
4.3.34. Hyp Debug Configuration Register
4.3.35. Hyp Coprocessor Trap Register
4.3.36. Hyp Auxiliary Configuration Register
4.3.37. Translation Table Base Register 0 and Register 1
4.3.38. Translation Table Base Control Register
4.3.39. Hyp Translation Control Register
4.3.40. Data Fault Status Register
4.3.41. Instruction Fault Status Register
4.3.42. Auxiliary Data Fault Status Register
4.3.43. Auxiliary Instruction Fault Status Register
4.3.44. Hyp Auxiliary Data Fault Syndrome Register
4.3.45. Hyp Auxiliary Instruction Fault Syndrome Register
4.3.46. Hyp Syndrome Register
4.3.47. Physical Address Register
4.3.48. L2 Control Register
4.3.49. L2 Extended Control Register
4.3.50. Memory Attribute Indirection Register 0
4.3.51. Memory Attribute Indirection Register 1
4.3.52. Auxiliary Memory Attribute Indirection Register 0
4.3.53. Auxiliary Memory Attribute Indirection Register 1
4.3.54. Hyp Auxiliary Memory Attribute Indirection Register 0
4.3.55. Hyp Auxiliary Memory Attribute Indirection Register 1
4.3.56. FCSE Process ID Register
4.3.57. Instruction L1 Data n Register
4.3.58. Data L1 Data n Register
4.3.59. RAM Index Register
4.3.60. L2 Auxiliary Control Register
4.3.61. L2 Prefetch Control Register
4.3.62. Auxiliary Control Register 2
4.3.63. Configuration Base Address Register
4.3.64. CPU Memory Error Syndrome Register
4.3.65. L2 Memory Error Syndrome Register
5. Memory Management Unit
5.1. About the MMU
5.2. TLB organization
5.2.1. L1 instruction TLB
5.2.2. L1 data TLB
5.2.3. L2 TLB
5.3. TLB match process
5.4. Memory access sequence
5.5. MMU enabling and disabling
5.6. Intermediate table walk caches
5.7. External aborts
5.7.1. External aborts on data read or write
5.7.2. Synchronous and asynchronous aborts
6. Level 1 Memory System
6.1. About the L1 memory system
6.2. Cache organization
6.3. L1 instruction memory system
6.3.1. Instruction cache disabled behavior
6.3.2. Instruction cache speculative memory accesses
6.3.3. Fill buffers
6.3.4. Non-cacheable fetching
6.3.5. Parity error handling
6.3.6. Cache line length and heterogeneous systems
6.4. L1 data memory system
6.4.1. Behavior for different memory types
6.4.2. Coherence
6.4.3. Cache disabled behavior
6.4.4. Non-cacheable streaming enhancement
6.4.5. Synchronization primitives
6.4.6. LDRT and STRT instructions
6.4.7. Preload instruction behavior
6.4.8. Error Correction Code
6.5. Program flow prediction
6.5.1. Predicted and non-predicted instructions
6.5.2. Return stack predictions
6.5.3. Indirect predictor
6.5.4. Static predictor
6.5.5. Enabling program flow prediction
6.6. L1 RAM memories
7. Level 2 Memory System
7.1. About the L2 memory system
7.2. Cache organization
7.2.1. L2 cache bank structure
7.2.2. Strictly-enforced inclusion property with L1 data caches
7.2.3. Enabling and disabling the L2 cache
7.2.4. Error Correction Code
7.2.5. Register slice support for large cache sizes
7.3. L2 RAM memories
7.4. L2 cache prefetcher
7.5. Cache coherency
7.6. Asynchronous errors
7.7. ACE
7.7.1. L2 memory interface attributes
7.7.2. ARID and AWID
7.7.3. ACE transfers
7.7.4. Distributed virtual memory transactions
7.7.5. Cache maintenance transactions
7.7.6. Snoop filter support
7.7.7. ACE configurations
7.7.8. ACE configuration signals
7.8. ACP
7.8.1. Burst support
7.8.2. ACP user bits
8. Generic Interrupt Controller
8.1. About the Generic Interrupt Controller
8.2. GIC functional description
8.2.1. GIC clock frequency
8.2.2. GIC memory-map
8.2.3. Interrupt sources
8.2.4. Interrupt priority levels
8.2.5. GIC configuration
8.3. GIC programmers model
8.3.1. Distributor register summary
8.3.2. Distributor register descriptions
8.3.3. CPU interface register summary
8.3.4. CPU interface register descriptions
8.3.5. Virtual interface control register summary
8.3.6. Virtual interface control register descriptions
8.3.7. Virtual CPU interface register summary
8.3.8. Virtual CPU interface register descriptions
9. Generic Timer
9.1. About the Generic Timer
9.2. Generic Timer functional description
9.3. Generic Timer programmers model
10. Debug
10.1. About debug
10.1.1. Debug host
10.1.2. Protocol converter
10.1.3. Debug target
10.1.4. The debug unit
10.2. Debug register interfaces
10.2.1. Processor interfaces
10.2.2. Breakpoints and watchpoints
10.2.3. Effects of resets on debug registers
10.3. Debug register summary
10.4. Debug register descriptions
10.4.1. Debug ID Register
10.4.2. Program Counter Sampling Register
10.4.3. Debug Run Control Register
10.4.4. Debug External Auxiliary Control Register
10.4.5. Breakpoint Value Registers
10.4.6. Breakpoint Control Registers
10.4.7. Watchpoint Value Registers
10.4.8. Watchpoint Control Registers
10.4.9. Debug ROM Address Register
10.4.10. Breakpoint Extended Value Registers
10.4.11. OS Lock Access Register
10.4.12. OS Lock Status Register
10.4.13. Device Powerdown and Reset Control Register
10.4.14. Debug Self Address Offset Register
10.4.15. Integration Output Control Register
10.4.16. Integration Input Status Register
10.4.17. Integration Mode Control Register
10.4.18. Claim Tag Set Register
10.4.19. Claim Tag Clear Register
10.4.20. Debug Device ID Register 0
10.4.21. Peripheral Identification Registers
10.4.22. Component Identification Registers
10.5. Debug events
10.5.1. Watchpoint debug events
10.5.2. Asynchronous aborts
10.5.3. Debug OS Lock
10.6. External debug interface
10.6.1. Memory map
10.6.2. Miscellaneous debug signals
10.6.3. Changing the authentication signals
11. Performance Monitor Unit
11.1. About the PMU
11.2. PMU functional description
11.2.1. Event interface
11.2.2. CP15 and APB interface
11.2.3. Counters
11.3. PMU register summary
11.4. PMU register descriptions
11.4.1. Performance Monitor Configuration Register
11.4.2. Performance Monitor Control Register
11.4.3. Performance Monitor Common Event Identification Register 0
11.4.4. Performance Monitor Common Event Identification Register 1
11.4.5. Peripheral Identification Registers
11.4.6. Component Identification Registers
11.5. Effect of debug double lock on PMU register access
11.6. Events
11.7. Interrupts
11.8. Exporting PMU events
11.8.1. External hardware
11.8.2. Debug trace hardware
12. Program Trace Macrocell
12.1. About PTM
12.2. PTM options
12.3. PTM functional description
12.3.1. Processor interface
12.3.2. Trace generation
12.3.3. Filtering and triggering resources
12.3.4. FIFO
12.3.5. Trace out
12.4. Reset
12.5. PTM programmers model
12.5.1. Modes of operation
12.5.2. Register short names
12.5.3. Event definitions
12.5.4. Turning off the PTM
12.5.5. Interaction with the performance monitoring unit
12.5.6. Effect of debug double lock on trace register access
12.6. Register summary
12.7. Register descriptions
12.7.1. Main Control Register
12.7.2. Configuration Code Register
12.7.3. System Configuration Register
12.7.4. TraceEnable Start/Stop Control Register
12.7.5. TraceEnable Control Register 1
12.7.6. Synchronization Frequency Register
12.7.7. ETM ID Register
12.7.8. Configuration Code Extension Register
12.7.9. Extended External Input Selection Register
12.7.10. Auxiliary Control Register
12.7.11. Power Down Control Register
12.7.12. Miscellaneous Output Register
12.7.13. Miscellaneous Input Register
12.7.14. Trigger Register
12.7.15. ATB Data Register 0
12.7.16. ATB Control Register 2
12.7.17. ATB Identification Register
12.7.18. ATB Control Register 0
12.7.19. Integration Mode Control Register
12.7.20. Peripheral Identification Registers
12.7.21. Component Identification Registers
13. Cross Trigger
13.1. About the cross trigger
13.2. Trigger inputs and outputs
13.3. Cortex-A15 CTI
13.4. Cortex-A15 CTM
14. NEON and VFP Unit
14.1. About NEON and VFP unit
14.1.1. Advanced SIMDv2 support
14.1.2. VFPv4 support
14.2. Programmers model for NEON and VFP unit
14.2.1. Accessing the Advanced SIMD and VFP feature identification registers
14.2.2. Enabling Advanced SIMD and VFP extensions
14.2.3. Register summary
14.2.4. Register descriptions
A. Signal Descriptions
A.1. About the signal descriptions
A.2. Clock signals
A.3. Reset signals
A.4. Configuration signals
A.5. Generic Interrupt Controller signals
A.6. Generic Timer signals
A.7. WFE and WFI standby signals
A.8. Power management signals
A.9. AXI interfaces
A.9.1. AXI master interface signals
A.9.2. ACP signals
A.10. External debug interface
A.10.1. APB interface signals
A.10.2. Authentication interface signals
A.10.3. Miscellaneous debug signals
A.11. PTM interface
A.11.1. ATB interface
A.11.2. Miscellaneous PTM interface
A.12. Cross trigger channel interface
A.13. PMU signals
A.14. DFT and MBIST interfaces
A.14.1. DFT interface
A.14.2. MBIST interface
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. Example multiprocessor configuration
2.1. Block diagram
2.2. ACLKENM with CLK:ACLKM ratio changing from 3:1 to 1:1
2.3. ACLKENS with CLK:ACLKS ratio changing from 3:1 to 1:1
2.4. PCLKENDBG with PCLKDBG:internal PCLKDBG ratio changing from 2:1 to 1:1
2.5. ATCLKEN with CLK:ATCLK ratio at 2:1
2.6. PERIPHCLKEN with CLK:internal IC clock ratio at 2:1
2.7. Power-on reset timing
2.8. Soft reset timing
2.9. NEON and VFP reset timing
2.10. Debug CLK reset timing
2.11. Debug PCLKDBG reset timing
2.12. STANDBYWFI deassertion timing
2.13. L2 Wait For Interrupt timing
2.14. WFI successful retention timing
2.15. WFI denied retention timing
2.16. Power domains
3.1. JIDR bit assignments
4.1. MIDR bit assignments
4.2. CTR bit assignments
4.3. TLBTR bit assignments
4.4. MPIDR bit assignments
4.5. REVIDR bit assignments
4.6. ID_PFR0 bit assignments
4.7. ID_PFR1 bit assignments
4.8. ID_DFR0 bit assignments
4.9. ID_MMFR0 bit assignments
4.10. ID_MMFR1 bit assignments
4.11. ID_MMFR2 bit assignments
4.12. ID_MMFR3 bit assignments
4.13. ID_ISAR0 bit assignments
4.14. ID_ISAR1 bit assignments
4.15. ID_ISAR2 bit assignments
4.16. ID_ISAR3 bit assignments
4.17. ID_ISAR4 bit assignments
4.18. CCSIDR bit assignments
4.19. CLIDR bit assignments
4.20. CSSELR bit assignments
4.21. VPIDR bit assignments
4.22. VMPIDR bit assignments
4.23. SCTLR bit assignments
4.24. ACTLR bit assignments
4.25. CPACR bit assignments
4.26. SCR bit assignments
4.27. NSACR bit assignments
4.28. HSCTLR bit assignments
4.29. HDCR bit assignments
4.30. HCPTR bit assignments
4.31. DFSR bit assignments for Short-descriptor translation table format
4.32. DFSR bit assignments for Long-descriptor translation table format
4.33. IFSR bit assignments for Short-descriptor translation table format
4.34. IFSR bit assignments for Long-descriptor translation table format
4.35. ADFSR bit assignments
4.36. HADFSR bit assignments
4.37. HSR bit assignments
4.38. L2CTLR bit assignments
4.39. L2ECTLR bit assignments
4.40. IL1Datan bit assignments
4.41. DL1Datan bit assignments
4.42. RAMINDEX bit assignments
4.43. RAMINDEX bit assignments for L1-I tag RAM
4.44. RAMINDEX bit assignments for L1-I data RAM
4.45. RAMINDEX bit assignments for L1-I BTB RAM
4.46. RAMINDEX bit assignments for L1-I GHB RAM
4.47. RAMINDEX bit assignments for L1-I TLB array
4.48. RAMINDEX bit assignments for L1-I indirect predictor RAM
4.49. RAMINDEX bit assignments for L1-D tag RAM
4.50. RAMINDEX bit assignments for L1-D data RAM
4.51. RAMINDEX bit assignments for L1-D load TLB array
4.52. RAMINDEX bit assignments for L1-D store TLB array
4.53. RAMINDEX bit assignments for L2 tag RAM
4.54. RAMINDEX bit assignments for L2 data RAM
4.55. RAMINDEX bit assignments for L2 snoop tag RAM
4.56. RAMINDEX bit assignments for L2 data ECC RAM
4.57. RAMINDEX bit assignments for L2 dirty RAM
4.58. RAMINDEX bit assignments for L2 TLB RAM
4.59. L2ACTLR bit assignments
4.60. L2PFR bit assignments
4.61. ACTLR2 bit assignments
4.62. CBAR bit assignments
4.63. CPUMERRSR bit assignments
4.64. L2MERRSR bit assignments
7.1. L2 cache bank structure
8.1. GICD_TYPER bit assignments
8.2. GICD_IIDR bit assignments
8.3. GICD_PPISR bit assignments
8.4. GICD_SPISR bit assignments
8.5. GICD_SPISR address map
8.6. GICC_IIDR bit assignments
8.7. GICH_VTR bit assignments
10.1. Typical debug system
10.2. DBGDIDR bit assignments
10.3. DBGPCSR bit assignments
10.4. DBGDRCR bit assignments
10.5. DBGEACR bit assignments
10.6. DBGBVR bit assignments
10.7. DBGBCR bit assignments
10.8. DBGWVR bit assignments
10.9. DBGWCR bit assignments
10.10. DBGDRAR 32-bit register bit assignments
10.11. DBGDRAR 64-bit register bit assignments
10.12. DBGBXVR bit assignments
10.13. DBGOSLAR bit assignments
10.14. DBGOSLSR bit assignments
10.15. DBGPRCR bit assignments
10.16. DBGDSAR 32-bit register bit assignments
10.17. DBGDSAR 64-bit register bit assignments
10.18. DBGITOCTRL bit assignments
10.19. DBGITISR bit assignments
10.20. DBGITCTRL bit assignments
10.21. DBGCLAIMSET bit assignments
10.22. DBGCLAIMCLR bit assignments
10.23. DBGDEVID0 bit assignments
10.24. External debug interface, including APBv3 slave port
11.1. PMU block diagram
11.2. PMCFGR bit assignments
11.3. PMCR bit assignments
12.1. PTM functional blocks
12.2. ETMCR bit assignments
12.3. ETMCCR bit assignments
12.4. ETMSCR bit assignments
12.5. ETMSSCR bit assignments
12.6. ETMECR1 bit assignments
12.7. ETMIDR bit assignments
12.8. ETMCCER bit assignments
12.9. ETMEXTINSELR bit assignments
12.10. ETMAUXCR bit assignments
12.11. ETMPDCR bit assignments
12.12. ITMISCOUT bit assignments
12.13. ITMISCIN bit assignments
12.14. ITTRIGGER bit assignments
12.15. ITATBDATA0 bit assignments
12.16. ITATBCTR2 bit assignments
12.17. ITATBID bit assignments
12.18. ITATBCTR0 bit assignments
13.1. Debug system components
14.1. FPSID bit assignments
14.2. FPSCR bit assignments
14.3. MVFR1 bit assignments
14.4. MVFR0 bit assignments
14.5. FPEXC bit assignments

List of Tables

1.1. Cortex-A15 MPCore processor configurable options
1.2. Valid combinations of L2 tag and data RAM register slice
2.1. Areas controlled by reset signals
2.2. Valid reset combinations
2.3. Valid power modes
3.1. Summary of Jazelle Extension registers
3.2. JIDR bit assignments
3.3. CPSR J and T bit encoding
4.1. Column headings definition for CP15 register summary tables
4.2. c0 register summary
4.3. c1 register summary
4.4. c2 register summary
4.5. c3 register summary
4.6. c5 register summary
4.7. c6 register summary
4.8. c7 register summary
4.9. c8 register summary
4.10. c9 register summary
4.11. c10 register summary
4.12. c12 register summary
4.13. c13 register summary
4.14. c15 register summary
4.15. 64-bit register summary
4.16. Identification registers
4.17. Virtual memory registers
4.18. PL1 Fault handling registers
4.19. Other system control registers
4.20. Cache and branch predictor maintenance operations
4.21. TLB maintenance operations
4.22. Address translation operations
4.23. Miscellaneous system control operations
4.24. Performance monitor registers
4.25. Security Extensions registers
4.26. Virtualization Extensions registers
4.27. Hyp mode TLB maintenance operations
4.28. Implementation defined registers
4.29. MIDR bit assignments
4.30. CTR bit assignments
4.31. TLBTR bit assignments
4.32. MPIDR bit assignments
4.33. REVIDR bit assignments
4.34. ID_PFR0 bit assignments
4.35. ID_PFR1 bit assignments
4.36. ID_DFR0 bit assignments
4.37. ID_MMFR0 bit assignments
4.38. ID_MMFR1 bit assignments
4.39. ID_MMFR2 bit assignments
4.40. ID_MMFR3 bit assignments
4.41. ID_ISAR0 bit assignments
4.42. ID_ISAR1 bit assignments
4.43. ID_ISAR2 bit assignments
4.44. ID_ISAR3 bit assignments
4.45. ID_ISAR4 bit assignments
4.46. CCSIDR bit assignments
4.47. Encodings of the Cache Size ID Register
4.48. CLIDR bit assignments
4.49. CSSELR bit assignments
4.50. VPIDR bit assignments
4.51. VMPIDR bit assignments
4.52. SCTLR bit assignments
4.53. ACTLR bit assignments
4.54. CPACR bit assignments
4.55. SCR bit assignments
4.56. NSACR bit assignments
4.57. HSCTLR bit assignments
4.58. HDCR bit assignments
4.59. HCPTR bit assignments
4.60. DFSR bit assignments for Short-descriptor translation table format
4.61. DFSR bit assignments for Long-descriptor translation table format
4.62. Encodings of LL bits associated with the MMU fault
4.63. IFSR bit assignments for Short-descriptor translation table format
4.64. IFSR bit assignments for Long-descriptor translation table format
4.65. Encodings of LL bits associated with the MMU fault
4.66. ADFSR bit assignments
4.67. HADFSR bit assignments
4.68. HSR bit assignments
4.69. L2CTLR bit assignments
4.70. L2ECTLR bit assignments
4.71. IL1Datan bit assignments
4.72. DL1Datan bit assignments
4.73. RAMINDEX bit assignments
4.74. L2ACTLR bit assignments
4.75. L2 Prefetch Control Register bit assignments
4.76. Auxiliary Control Register 2 bit assignments
4.77. CBAR bit assignments
4.78. CPUMERRSR bit assignments
4.79. L2MERRSR bit assignments
6.1. Memory attribute combinations
6.2. L1 RAM memories
7.1. L2 tag RAM latency with slice and setup factored in
7.2. L2 data RAM latency with slice and setup factored in
7.3. L2 RAM memories
7.4. L2 memory interface attributes
7.5. Supported ACE configurations
7.6. Supported features in the ACE configurations
8.1. Cortex-A15 MPCore GIC memory map
8.2. GIC configurable options
8.3. Distributor register summary
8.4. GICD_TYPER bit assignments
8.5. GICD_IIDR bit assignments
8.6. PPI implementation
8.7. GICD_PPISR bit assignments
8.8. GICD_SPISR bit assignments
8.9. CPU interface register summary
8.10. Active Priority Register implementation
8.11. GICC_IIDR bit assignments
8.12. Virtual interface control register summary
8.13. GICH_VTR bit assignments
8.14. Virtual CPU interface register summary
9.1. Generic Timer signals
9.2. Generic Timer registers
10.1. CP14 debug register summary
10.2. DBGDIDR bit assignments
10.3. DBGPCSR bit assignments
10.4. DBGDRCR bit assignments
10.5. DBGEACR bit assignments
10.6. DBGBVR bit assignments when register is used for address comparison
10.7. Breakpoint Value Register bit assignments when register is used for Context ID comparison
10.8. DBGBCR bit assignments
10.9. DBGWVR bit assignments
10.10. DBGWCR bit assignments
10.11. DBGDRAR bit assignments
10.12. DBGBXVR bit assignments
10.13. DBGOSLAR bit assignments
10.14. DBGOSLSR bit assignments
10.15. DBGPRCR bit assignments
10.16. DBGDSAR bit assignments
10.17. DBGITOCTRL bit assignments
10.18. DBGITISR bit assignments
10.19. DBGITCTRL bit assignments
10.20. DBGCLAIMSET bit assignments
10.21. DBGCLAIMCLR bit assignments
10.22. DBGDEVID0 bit assignments
10.23. Summary of the Peripheral Identification Registers
10.24. Summary of the Component Identification Registers
10.25. Address mapping for debug trace components
11.1. PMU register summary
11.2. PMCFGR bit assignments
11.3. PMCR bit assignments
11.4. Common Event Identification Register 0 bit assignments
11.5. Summary of the Peripheral Identification Registers
11.6. Summary of the Component Identification Registers
11.7. PMU events
12.1. Cortex-A15 MPCore PTM implementation options
12.2. Examples of register short names
12.3. Event resource definitions
12.4. PTM register summary
12.5. ETMCR bit assignments
12.6. ETMCCR bit assignments
12.7. ETMSCR bit assignments
12.8. ETMSSCR bit assignments
12.9. ETMECR1 bit assignments
12.10. ID Register bit assignments
12.11. ETMCCER bit assignments
12.12. ETMEXTINSELR bit assignments
12.13. ETMAUXCR bit assignments
12.14. ETMPDCR bit assignments
12.15. ITMISCOUT bit assignments
12.16. ITMISCIN bit assignments
12.17. ITTRIGGER bit assignments
12.18. ITATBDATA0 bit assignments
12.19. ITATBCTR2 bit assignments
12.20. ITATBID bit assignments
12.21. ITATBCTR0 bit assignments
12.22. Summary of the Peripheral ID Registers
12.23. Summary of the Component Identification Registers
13.1. Trigger inputs
13.2. Trigger outputs
14.1. Combinations of Advanced SIMD and VFP extensions
14.2. Advanced SIMD and VFP feature identification registers
14.3. Advanced SIMD and VFP system registers
14.4. FPSID bit assignments
14.5. FPSCR bit assignments
14.6. MVFR1 bit assignments 
14.7. MVFR0 bit assignments 
14.8. FPEXC bit assignments 
A.1. Clock and clock enable signals
A.2. Reset signals
A.3. Configuration signals
A.4. GIC signals
A.5. Generic Timer signals
A.6. WFE and WFI standby signals
A.7. Power management signals
A.8. Clock and configuration signals
A.9. Asynchronous error signals
A.10. Write address channel signals
A.11. Write data channel signals
A.12. Write response channel signals
A.13. Read address channel signals
A.14. Read data channel signals
A.15. Snoop address channel signals
A.16. Snoop data channel signals
A.17. Snoop response channel signals
A.18. Read/write acknowledge signals
A.19. Clock and configuration signals
A.20. Write address channel signals
A.21. Write data channel signals
A.22. Write response channel signals
A.23. Read address channel signals
A.24. Read data channel signals
A.25. APB interface signals
A.26. Authentication interface signals
A.27. Miscellaneous debug signals
A.28. ATB interface signals
A.29. Miscellaneous PTM interface signals
A.30. Cross trigger channel interface signals
A.31. Performance monitoring signals
A.32. DFT interface signals
A.33. L1 MBIST interface signals
A.34. L2 MBIST interface signals
B.1. Issue A
B.2. Differences between Issue A and issue B
B.3. Differences between Issue B and issue C
B.4. Differences between Issue C and issue D
B.5. Differences between Issue D and issue E
B.6. Differences between Issue E and issue F

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Revision History
Revision A26 April 2011First release for r0p0
Revision B29 July 2011First release for r1p0
Revision C28 September 2011First release for r2p0
Revision D16 December 2011First release for r2p1
Revision E20 March 2012First release for r3p0
Revision F04 May 2012First release for r3p1
Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438F
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