4.3.48. L2 Control Register

The L2CTLR characteristics are:

Purpose

Provides control options for the L2 memory system and ECC/parity support.

Usage constraints

The L2CTLR is:

  • A read/write register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher, with access rights that depend on the mode:

    • Read/write in Secure PL1 modes with some bits that are read-only.

    • Read-only and write-ignored in Non-secure PL1 and PL2 modes.

  • This register can only be written when the L2 memory system is idle. ARM recommends that you write to this register after a powerup reset before the MMU is enabled and before any ACE or ACP traffic has begun.

    If the register must be modified after a powerup reset sequence, to idle the L2 memory system, you must take the following steps:

    1. Disable the MMU from each processor followed by an ISB to ensure the MMU disable operation is complete, then followed by a DSB to drain previous memory transactions.

    2. Ensure that the system has no outstanding AC channel coherence requests to the Cortex-A15 MPCore processor.

    3. Ensure that the system has no outstanding ACP requests to the Cortex-A15 MPCore processor.

When the L2 is idle, the processor can update the L2CTLR followed by an ISB. After the L2CTLR is updated, the MMUs can be enabled and normal ACE and ACP traffic can resume.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.10.

Figure 4.38 shows the L2CTLR bit assignments.

Figure 4.38. L2CTLR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.69 shows the L2CTLR bit assignments.

Table 4.69. L2CTLR bit assignments

BitsNameFunction
[31]L2RSTDISABLE monitor

Monitors the L2 hardware reset disable pin, L2RSTDISABLE:

0

L2 valid RAM contents are reset by hardware.

1

L2 valid RAM contents are not reset by hardware.

This bit is read-only and the reset value is determined by the primary input, L2RSTDISABLE.

[30:26]-

Reserved, RAZ/WI.

[25:24]Number of processors

Number of processors present:

b00

One processor, CPU0.

b01

Two processors, CPU0 and CPU1.

b10

Three processors, CPU0, CPU1, and CPU2.

b11

Four processors, CPU0, CPU1, CPU2, and CPU3.

These bits are read-only and the reset value of this field is set to the number of processors present in the configuration.

[23]Interrupt Controller

Interrupt Controller:

0

Interrupt Controller not present.

1

Interrupt Controller present.

This is a read-only bit and the reset value depends on whether the Interrupt Controller is present.

[22]-

Reserved, RAZ/WI.

[21]ECC and parity enable

ECC and parity enable bit in L1 and L2 caches:

0

Disables ECC and parity. This is the reset value.

1

Enables ECC and parity.

If ECC/parity is not implemented in L1 and L2 caches, this bit is RAZ/WI.

[20:13]-

Reserved, RAZ/WI.

[12]Tag RAM slice

L2 tag RAM slice:

0

0 slice.

1

1 slice.

This is a read-only bit and the reset value of this field is set to the number of tag RAM slice present in the configuration. See Register slice support for large cache sizes for more information.

[11:10]Data RAM slice

L2 data RAM slice:

b00

0 slice.

b01

1 slice.

b10

2 slices.

b11

Invalid value.

These are read-only bits and the reset value of this field is set to the number of data RAM slice present in the configuration. See Register slice support for large cache sizes for more information.

[9]Tag RAM setup

L2 tag RAM setup:

0

0 cycle. This the reset value.

1

1 cycle.

[8:6]Tag RAM latency

L2 tag RAM latency:

b000

2 cycles. This is the reset value.

b001

2 cycles.

b010

3 cycles.

b011

4 cycles.

b1xx

5 cycles, where x can be any value.

[5]Data RAM setup

L2 data RAM setup:

0

0 cycle. This the reset value.

1

1 cycle.

[4:3]-

Reserved, RAZ/WI.

[2:0]Data RAM latency

L2 data RAM latency:

b000

2 cycles. This is the reset value.

b001

2 cycles.

b010

3 cycles.

b011

4 cycles.

b100

5 cycles.

b101

6 cycles.

b110

7 cycles.

b111

8 cycles.


To access the L2CTLR, read or write the CP15 register with:

MRC p15, 1, <Rt>, c9, c0, 2; Read L2 Control Register
MCR p15, 1, <Rt>, c9, c0, 2; Write L2 Control Register
Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G
Non-ConfidentialID080412