8.3.1. Distributor register summary

The Distributor centralizes all interrupt sources, determines the priority of each interrupt, and for each CPU interface dispatches the interrupt with the highest priority to the interface for priority masking and preemption handling.

The Distributor provides a programming interface for:

In addition, the Distributor provides:

The Distributor provides the ability to set interrupts as either:

See the ARM Generic Interrupt Controller (GIC) Architecture Specification for information on interrupt grouping.

Table 8.3 shows the register map for the Distributor. The offsets in this table are relative to the Distributor block base address as shown in Table 8.1.

The GICD_IPR and GICD_IPTR registers are byte-accessible and word-accessible. All other registers in Table 8.3 are word-accessible. Registers not described in Table 8.3 are RAZ/WI.

Table 8.3. Distributor register summary

Offset NameTypeResetDescription
0x000GICD_CTLRRW[a]0x00000000Distributor Control Register, see ARM Generic Interrupt Controller Architecture Specification
0x004GICD_TYPERROConfiguration dependentInterrupt Controller Type Register
0x008GICD_IIDRRO0x0000043BDistributor Implementer Identification Register
0x080 - 0x09CGICD_IGROUPRnRW[b]0x00000000Interrupt Group Registers, see ARM Generic Interrupt Controller Architecture Specification
0x100 GICD_ISENABLERnRW0x0000FFFF[c]Interrupt Set-Enable Registers, see ARM Generic Interrupt Controller Architecture Specification
0x104 - 0x11C0x00000000
0x180GICD_ICENABLERnRW0x0000FFFF[c]Interrupt Clear-Enable Registers, see ARM Generic Interrupt Controller Architecture Specification
0x184 - 0x19C0x00000000
0x200 - 0x21CGICD_ISPENDRnRW0x00000000Interrupt Set-Pending Registers, see ARM Generic Interrupt Controller Architecture Specification
0x280 - 0x29CGICD_ICPENDRnRW0x00000000Interrupt Clear-Pending Registers, see ARM Generic Interrupt Controller Architecture Specification
0x300 - 0x31CGICD_ISACTIVERnRW0x00000000Interrupt Set-Active Registers, see ARM Generic Interrupt Controller Architecture Specification
0x380 - 0x39CGICD_ICACTIVERnRW0x00000000Interrupt Clear-Active Registers, see ARM Generic Interrupt Controller Architecture Specification
0x400 - 0x4FCGICD_IPRIORITYRnRW0x00000000Interrupt Priority Registers, see ARM Generic Interrupt Controller Architecture Specification
0x800 - 0x81CGICD_ITARGETSRnRO[d]Configuration dependentInterrupt Processor Targets Registers, see ARM Generic Interrupt Controller Architecture Specification
0x820 - 0x8FCRW[d]0x00000000
0xC00GICD_ICFGRnRO0xAAAAAAAA[e]Interrupt Configuration Register
0xC04RO0x55540000[e]
0xC08 - 0xC3CRW0x55555555[e]
0xD00GICD_PPISRRO0x00000000Private Peripheral Interrupt Status Register
0xD04 -0xD1CGICD_SPISRnRO0x00000000

Shared Peripheral Interrupt Status Registers

0xF00GICD_SGIRWO-Software Generated Interrupt Register, see ARM Generic Interrupt Controller Architecture Specification
0xF10 - 0xF1CGICD_CPENDSGIRnRW0x00000000SGI Clear-Pending Registers, see ARM Generic Interrupt Controller Architecture Specification
0xF20 - 0xF2CGICD_SPENDSGIRnRW0x00000000SGI Set-Pending Registers, see ARM Generic Interrupt Controller Architecture Specification
0xFD0GICD_PIDR4RO0x04Peripheral ID4 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFD4GICD_PIDR5RO0x00Peripheral ID5 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFD8GICD_PIDR6RO0x00Peripheral ID6 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFDCGICD_PIDR7RO0x00Peripheral ID7 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFE0GICD_PIDR0RO0x90Peripheral ID0 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFE4GICD_PIDR1RO0xB4Peripheral ID1 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFE8GICD_PIDR2RO0x2BPeripheral ID2 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFECGICD_PIDR3RO0x00Peripheral ID3 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFF0GICD_CIDR0RO0x0DComponent ID0 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFF4GICD_CIDR1RO0xF0Component ID1 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFF8GICD_CIDR2RO0x05Component ID2 Register, see ARM Generic Interrupt Controller Architecture Specification
0xFFCGICD_CIDR3RO0xB1Component ID3 Register, see ARM Generic Interrupt Controller Architecture Specification

[a] You cannot modify the secure copy of this register if CFGSDISABLE is asserted.

[b] This register is only accessible with a Secure access.

[c] The reset value for the register that contains the SGI and PPI interrupts is 0x0000FFFF because SGIs are always enabled.

[d] The register that contains the SGI and PPI interrupts is read-only and the reset value is configuration-dependent. For Cortex-A15 configurations with only one processor, these registers are RAZ/WI.

[e] The reset value for the register that contains the SGI interrupts is 0xAAAAAAAA. The reset value for the register that contains the PPI interrupts is 0x55540000. The reset value for the registers that contain the SPI interrupts is 0x55555555.


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