Cortex-A15 MPCore Technical Reference Manual: 4.3.35. Hyp Coprocessor Trap Register

4.3.35. Hyp Coprocessor Trap Register

The HCPTR characteristics are:

Purpose

Controls the trapping to Hyp mode of Non-secure accesses, at PL1 or lower, to functions provided coprocessors other than CP14 and CP15. The HCPTR also controls the access to floating-point and Advanced SIMD functionality from Hyp mode.

Note

Accesses to floating-point and Advanced SIMD functionality from Hyp mode:

Are not affected by settings in the CPACR. See Coprocessor Access Control Register.
Are affected by settings in the NSACR. See Non-Secure Access Control Register. The NSACR settings take precedence over the HCPTR settings. See the Usage constraints for more information.

Usage constraints

The HCPTR is:

A read/write register.
Only accessible from Hyp mode or from Monitor mode when SCR.NS is 1.
If a bit in the NSACR prohibits a Non-secure access, then the corresponding bit in the HCPTR behaves as RAO/WI for Non-secure accesses. See the bit descriptions for more information.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.30 shows the HCPTR bit assignments.

Figure 4.30. HCPTR bit assignments

Table 4.59 shows the HCPTR bit assignments.

Table 4.59. HCPTR bit assignments

Bits	Name	Function
[31]	TCPAC	Trap Coprocessor Access Control Register accesses: 0 Has no effect on CPACR accesses. 1 Trap valid Non-secure PL1 CPACR accesses to Hyp mode. When this bit is set to 1, any valid Non-secure PL1 or PL0 access to the CPACR is trapped to Hyp mode. See the ARM Architecture Reference Manual for more information.
[30:16]	-	Reserved, UNK/SBZP.
[15]	TASE	Trap Advanced SIMD Extension use: 0 If the NSACR settings permit Non-secure use of the Advanced SIMD functionality then Hyp mode can access that functionality, regardless of any settings in the CPACR. Note This bit value has no effect on possible use of the Advanced SIMD functionality from Non-secure PL1 and PL0 modes. 1 Trap valid Non-secure accesses to Advanced SIMD functionality to Hyp mode. When this bit is set to 1, any otherwise-valid access to Advanced SIMD functionality from: A Non-secure PL1 or PL0 mode is trapped to Hyp mode. Hyp mode generates an Undefined Instruction exception, taken in Hyp mode. Note If TCP10 and TCP11 are set to 1, then all Advanced SIMD use is trapped to Hyp mode, regardless of the value of this field. If VFP is implemented and NEON is not implemented, this bit is RAO/WI. If VFP and NEON are not implemented, this bit is RAO/WI. If NSACR.NSASEDIS is set to 1, then on Non-secure accesses to the HCPTR, the TASE bit behaves as RAO/WI.
[14]	-	Reserved, RAZ/WI.
[13:12]	-	Reserved, RAO/WI.
[11]	TCP11	Trap coprocessor 11: 0 If NSACR.CP11 is set to 1, then Hyp mode can access CP11, regardless of the value of CPACR.CP11. Note This bit value has no effect on possible use of CP11 from Non-secure PL1 and PL0 modes. 1 Trap valid Non-secure accesses to CP11 to Hyp mode. When TCP11 is set to 1, any otherwise-valid access to CP11 from: A Non-secure PL1 or PL0 mode is trapped to Hyp mode. Hyp mode generates an Undefined Instruction exception, taken in Hyp mode. If VFP and NEON are not implemented, this bit is RAO/WI. See the ARM Architecture Reference Manual for more information.
[10]	TCP10	Trap coprocessor 10: 0 If NSACR.CP10 is set to 1, then Hyp mode can access CP10, regardless of the value of CPACR.CP10. Note This bit value has no effect on possible use of CP10 from Non-secure PL1 and PL0 modes. 1 Trap valid Non-secure accesses to CP10 to Hyp mode. When TCP10 is set to 1, any otherwise-valid access to CP10 from: A Non-secure PL1 or PL0 mode is trapped to Hyp mode. Hyp mode generates an Undefined Instruction exception, taken in Hyp mode. If VFP and NEON are not implemented, this bit is RAO/WI. See the ARM Architecture Reference Manual for more information.
[9:0]	-	Reserved, RAO/WI.

To access the HCPTR, read or write the CP15 register with:

MRC p15, 4, <Rt>, c1, c1, 2; Read Hyp Coprocessor Trap Register

MCR p15, 4, <Rt>, c1, c1, 2; Write Hyp Coprocessor Trap Register

Copyright © 2011-2012 ARM. All rights reserved.	ARM DDI 0438G
Non-Confidential	ID080412
PDF version