8.3.3. CPU interface register summary

Each CPU interface block provides the interface for a Cortex-A15 MPCore processor that operates with the GIC. Each CPU interface provides a programming interface for:

For more information on CPU interfaces, see the ARM Generic Interrupt Controller Architecture Specification.

Table 8.9 shows the register map for the CPU interface. The offsets in this table are relative to the CPU interface block base address as shown in Table 8.1.

All the registers in Table 8.9 are word-accessible. Registers not described in this table are RAZ/WI.

Table 8.9. CPU interface register summary

OffsetNameTypeResetDescription
0x0000GICC_CTLRRW0x00000000CPU Interface Control Register, see ARM Generic Interrupt Controller Architecture Specification
0x0004GICC_PMRRW0x00000000Interrupt Priority Mask Register, see ARM Generic Interrupt Controller Architecture Specification
0x0008GICC_BPRRW

0x00000002 (S)[a]

0x00000003 (NS)[b]

Binary Point Register, see ARM Generic Interrupt Controller Architecture Specification
0x000CGICC_IARRO0x000003FFInterrupt Acknowledge Register, see ARM Generic Interrupt Controller Architecture Specification
0x0010GICC_EOIRWO-End Of Interrupt Register, see ARM Generic Interrupt Controller Architecture Specification
0x0014GICC_RPRRO0x000000FFRunning Priority Register, see ARM Generic Interrupt Controller Architecture Specification
0x0018GICC_HPPIRRO0x000003FFHighest Priority Pending Interrupt Register, see ARM Generic Interrupt Controller Architecture Specification
0x001CGICC_ABPRRW[c]0x00000003Aliased Binary Point Register, see ARM Generic Interrupt Controller Architecture Specification
0x0020GICC_AIARRO[c]0x000003FF

Aliased Interrupt Acknowledge Register, see ARM Generic Interrupt Controller Architecture Specification

0x0024GICC_AEOIRWO[c]-

Aliased End of Interrupt Register, see ARM Generic Interrupt Controller Architecture Specification

0x0028GICC_AHPPIRRO[c]0x000003FF

Aliased Highest Priority Pending Interrupt Register, see ARM Generic Interrupt Controller Architecture Specification

0x00D0GICC_APR0RW0x00000000Active Priority Register
0x00E0GICC_NSAPR0RW[c]0x00000000Non-secure Active Priority Register
0x00FCGICC_IIDRRO0x0002043BCPU Interface Identification Register
0x1000GICC_DIRWO-Deactivate Interrupt Register, see ARM Generic Interrupt Controller Architecture Specification

[a] S = Secure.

[b] NS = Non-secure.

[c] This register is only accessible from a Secure access.


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