8.2.5. GIC configuration

Table 8.2 lists the configurable options for the GIC.

Table 8.2. GIC configurable options

FeatureRange of options
Generic Interrupt ControllerIncluded or Not
Shared Peripheral Interrupts0 to 224, in steps of 32

Bit[23] of the L2 Control Register indicates if the GIC is present or not, in the configuration. See L2 Control Register for more information.

If you configure the design to exclude the GIC, SPIs and the remaining GIC signals are not available, except PERIPHBASE[39:15]. PERIPHBASE[39:15] are retained, and the value can be read in the Configuration Base Address Register, to permit software to read the location of the GIC if it exists in the system external to the Cortex-A15 MPCore processor. See Configuration Base Address Register.

The Cortex-A15 MPCore processor always includes the virtual interrupt signals, nVIRQ and nVFIQ, regardless of whether the GIC is present or not. There is one nVIRQ and one nVFIQ for each processor. If you configure the processor to exclude the GIC, the input pins nVIRQ and nVFIQ can be tied off to HIGH if unused, or can be driven by an external GIC in the SoC.If you configure the processor to include the GIC, and the GIC is used, the input pins nVIRQ and nVFIQ must be tied off to HIGH. This is because the internal GIC generates the virtual interrupt signals to the processors. If you configure the processor to include the GIC, and the GIC is not used, the input pins nVIRQ and nVFIQ can be driven by an external GIC in the SoC.

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