6.6. L1 RAM memories

The L1 memory system contains several RAM memories that can be configured to use ECC or parity error detection mechanisms. Any RAM memory that uses ECC support can perform single bit error correction and double bit error detection. Contents of the RAM memories with parity support can invalidate entries if a parity error is detected because this data is associated with read-only structures.

Table 6.1 shows all RAM memories contained in the L1 memory system.

Table 6.2. L1 RAM memories

RAM memoryECC or Parity
L1 instruction tag RAMParity
L1 instruction data RAMParity
L1 instruction BTB RAMParity
L1 instruction GHB RAMNone
L1 instruction indirect predictor RAMNone
L1 data tag RAMECC
L1 data data RAMECC
L2 TLB RAM[a]Parity

[a] The L2 TLB RAM is a unified TLB structure that supports L1 instruction and L1 data TLB misses.

Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G