4.3.59. RAM Index Register

The RAMINDEX characteristics are:

Purpose

Read the instruction side L1 array contents into the IL1Datan register or read the data side L1 or L2 array contents into the DL1Datan register.

Usage constraints

The RAMINDEX is:

  • A write-only operation.

  • Any write to the RAMINDEX register must be followed by a DSB.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.14.

Figure 4.42 shows the RAMINDEX bit assignments.

Figure 4.42. RAMINDEX bit assignments

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Table 4.73 shows the RAMINDEX bit assignments.

Table 4.73. RAMINDEX bit assignments

BitsNameFunction
[31:24]RAMID

RAM Identifier. This field indicates which RAM is being accessed:

0x00

L1-I tag RAM.

0x01

L1-I data RAM.

0x02

L1-I BTB RAM.

0x03

L1-I GHB RAM.

0x04

L1-I TLB array.

0x05

L1-I indirect predictor RAM.

0x08

L1-D tag RAM.

0x09

L1-D data RAM.

0x0A

L1-D load-TLB array.

0x0B

L1-D store-TLB array.

0x10

L2 tag RAM.

0x11

L2 data RAM.

0x12

L2 snoop tag RAM.

0x13

L2 data ECC RAM.

0x14

L2 dirty RAM.

0x18

L2 TLB RAM.

[23:22]-

Reserved, RAZ/WI.

[21:18]Way

Indicates the way of the RAM that is being accessed.

[17:0]Index

Indicates the index address of the RAM that is being accessed.


Note

  • In Non-secure PL1 and PL2 modes, the RAMINDEX operation returns the contents of the RAM only if the entry is marked valid and Non-secure. Entries that are marked invalid or Secure update the IL1Datan or DL1Datan registers with 0x0 values.

  • In Secure PL1 modes, the RAMINDEX operation returns the contents of the RAM, regardless of whether the entry is marked valid or invalid, and Secure or Non-secure.

Note

  • The L1-I, L1-D, L2 TLB, and L2 snoop tag RAMs can only be accessed by the processor where the RAM resides or that owns the RAM.

  • The L2 tag, data, data ECC, and dirty RAMs can be accessed by any processor.

Figure 4.43 shows the RAMINDEX bit assignments for accessing L1-I tag RAM.

Figure 4.43. RAMINDEX bit assignments for L1-I tag RAM

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The RAMINDEX address bits for accessing L1-I tag RAM are:

Way

Way select.

VA[13:7]

Row select.

VA[6]

Bank select.

The data returned from accessing L1-I tag RAM are:

IL1DATA2

32'b0.

IL1DATA1

32'b0.

IL1DATA0

Tag data[31:0].

Figure 4.44 shows the RAMINDEX bit assignments for accessing L1-I data RAM.

Figure 4.44. RAMINDEX bit assignments for L1-I data RAM

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The RAMINDEX address bits for accessing L1-I data RAM are:

Way

Way select.

VA[13:6]

Set select.

VA[5:4]

Bank select.

VA[3]

Upper or lower doubleword within the quadword.

The data returned from accessing L1-I data RAM are:

IL1DATA2

Parity and auxiliary information.

IL1DATA1

Word1[31:0].

IL1DATA0

Word0[31:0].

Figure 4.45 shows the RAMINDEX bit assignments for accessing L1-I BTB RAM.

Figure 4.45. RAMINDEX bit assignments for L1-I BTB RAM

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The RAMINDEX address bits for accessing L1-I BTB RAM are:

Way

Way select.

VA[13:5]

Row select.

VA[4]

Bank select.

The data returned from accessing L1-I BTB RAM are:

IL1DATA2

BTB data[77:64].

IL1DATA1

BTB data[63:32].

IL1DATA0

BTB data[31:0].

Figure 4.46 shows the RAMINDEX bit assignments for accessing L1-I GHB RAM.

Figure 4.46. RAMINDEX bit assignments for L1-I GHB RAM

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The RAMINDEX address bits for accessing L1-I GHB RAM are:

Index[13:5]

Row select.

Index[4]

Bank select.

The data returned from accessing L1-I GHB RAM are:

IL1DATA2

32'b0.

IL1DATA1

GHB data[47:32].

IL1DATA0

GHB data[31:0].

Figure 4.47 shows the RAMINDEX bit assignments for accessing L1-I TLB array.

Figure 4.47. RAMINDEX bit assignments for L1-I TLB array

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The RAMINDEX address bits for accessing L1-I TLB array are:

TLB entry

Selects one of the 32 entries.

The data returned from accessing L1-I TLB array are:

IL1DATA2

TLB entry data[95:64].

IL1DATA1

TLB entry data[63:32].

IL1DATA0

TLB entry data[31:0].

Figure 4.48 shows the RAMINDEX bit assignments for accessing L1-I indirect predictor RAM.

Figure 4.48. RAMINDEX bit assignments for L1-I indirect predictor RAM

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The RAMINDEX address bits for accessing L1-I indirect predictor RAM are:

Index[7:0]

Indirect predictor entry.

The data returned from accessing L1-I indirect predictor RAM are:

IL1DATA2

32'b0.

IL1DATA1

32'b0.

IL1DATA0

Indirect predictor data[31:0].

Figure 4.49 shows the RAMINDEX bit assignments for accessing L1-D tag RAM.

Figure 4.49. RAMINDEX bit assignments for L1-D tag RAM

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The RAMINDEX address bits for accessing L1-D tag RAM are:

Way

Way select.

PA[13:8]

Row select.

PA[7:6]

Bank select.

The data returned from accessing L1-D tag RAM are:

DL1DATA3

32'b0.

DL1DATA2

32'b0.

DL1DATA1

Tag ECC[6:0].

DL1DATA0

Tag data[28:0].

Figure 4.50 shows the RAMINDEX bit assignments for accessing L1-D data RAM.

Figure 4.50. RAMINDEX bit assignments for L1-D data RAM

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The RAMINDEX address bits for accessing L1-D data RAM are:

Way

Way select.

PA[13:6]

Set select.

PA[5:4]

Bank select.

PA[3]

Upper or lower doubleword within the quadword.

The data returned from accessing L1-D data RAM are:

DL1DATA3

Word1 ECC[6:0].

DL1DATA2

Word0 ECC[6:0].

DL1DATA1

Word1 data[31:0].

DL1DATA0

Word0 data[31:0].

Figure 4.51 shows the RAMINDEX bit assignments for accessing L1-D load TLB array.

Figure 4.51. RAMINDEX bit assignments for L1-D load TLB array

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The RAMINDEX address bits for accessing L1-D load TLB array are:

TLB entry

Selects one of the 32 entries.

The data returned from accessing L1-D load TLB array are:

DL1DATA3

TLB entry data[101:96].

DL1DATA2

TLB entry data[95:64].

DL1DATA1

TLB entry data[63:32].

DL1DATA0

TLB entry data[31:0].

Figure 4.52 shows the RAMINDEX bit assignments for accessing L1-D store TLB array.

Figure 4.52. RAMINDEX bit assignments for L1-D store TLB array

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The RAMINDEX address bits for accessing L1-D store TLB array are:

TLB entry

Selects one of the 32 entries.

The data returned from accessing L1-D store TLB array are:

DL1DATA3

TLB entry data[101:96].

DL1DATA2

TLB entry data[95:64].

DL1DATA1

TLB entry data[63:32].

DL1DATA0

TLB entry data[31:0].

Figure 4.53 shows the RAMINDEX bit assignments for accessing L2 tag RAM.

Figure 4.53. RAMINDEX bit assignments for L2 tag RAM

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The RAMINDEX address bits for accessing L2 tag RAM are:

Way[3:0]

Way select.

PA[17:8]

Row select.

PA[7:6]

Tag bank select.

The data returned from accessing L2 tag RAM are:

DL1DATA3

32'b0.

DL1DATA2

32'b0.

DL1DATA1

Tag ECC[6:0].

DL1DATA0

Tag data[29:0].

Figure 4.54 shows the RAMINDEX bit assignments for accessing L2 data RAM.

Figure 4.54. RAMINDEX bit assignments for L2 data RAM

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The RAMINDEX address bits for accessing L2 data RAM are:

Way[3:0]

Way select.

PA[17:8]

Row select.

PA[7:6]

Tag bank select.

PA[5:4]

Data bank select.

The data returned from accessing L2 data RAM are:

DL1DATA3

Data[127:96].

DL1DATA2

Data[95:64].

DL1DATA1

Data[63:32].

DL1DATA0

Data[31:0].

Figure 4.55 shows the RAMINDEX bit assignments for accessing L2 snoop tag RAM.

Figure 4.55. RAMINDEX bit assignments for L2 snoop tag RAM

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The RAMINDEX address bits for accessing L2 snoop tag RAM are:

CPUID[1:0]

Processor ID of the executing processor that has access to the L2 snoop tag RAM.

Way

Way select.

PA[13:8]

Row select.

PA[7:6]

Bank select.

The data returned from accessing L2 snoop tag RAM are:

DL1DATA3

32'b0.

DL1DATA2

32'b0.

DL1DATA1

Tag ECC[6:0].

DL1DATA0

Tag data[28:0].

Figure 4.56 shows the RAMINDEX bit assignments for accessing L2 data ECC RAM.

Figure 4.56. RAMINDEX bit assignments for L2 data ECC RAM

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The RAMINDEX address bits for accessing L2 data ECC RAM are:

Way[3:0]

Way select.

PA[17:8]

Row select.

PA[7:6]

Tag bank select.

PA[5:4]

Data bank select.

The data returned from accessing L2 data ECC RAM are:

DL1DATA3

32'b0.

DL1DATA2

32'b0.

DL1DATA1

32'b0.

DL1DATA0

Data ECC[15:0].

Figure 4.57 shows the RAMINDEX bit assignments for accessing L2 dirty RAM.

Figure 4.57. RAMINDEX bit assignments for L2 dirty RAM

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The RAMINDEX address bits for accessing L2 dirty RAM are:

Way[3:0]

Way select.

PA[17:8]

Row select.

PA[7:6]

Tag bank select.

The data returned from accessing L2 dirty RAM are:

DL1DATA3

32'b0.

DL1DATA2

32'b0.

DL1DATA1

32'b0.

DL1DATA0

Dirty data[17:0].

Figure 4.58 shows the RAMINDEX bit assignments for accessing L2 TLB RAM.

Figure 4.58. RAMINDEX bit assignments for L2 TLB RAM

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The RAMINDEX address bits for accessing L2 TLB RAM are:

Way

Way select.

TLB entry

Selects one of the 128 entries in each way.

The data returned from accessing L2 TLB RAM are:

DL1DATA3

TLB entry data[99:96].

DL1DATA2

TLB entry data[95:64].

DL1DATA1

TLB entry data[63:32].

DL1DATA0

TLB entry data[31:0].

For example, to read one entry in the instruction side L1 data array:

LDR R0, =0x01000D80;
MCR p15, 0, R0, c15, c4, 0; Read I-L1 TLB data into IL1Data0-2
DSB
ISB
MRC p15, 0, R1, c15, c0, 0; Move IL1Data0 Register to R1
MRC p15, 0, R2, c15, c0, 1; Move IL1Data1 Register to R2
MRC p15, 0, R3, c15, c0, 2; Move IL1Data2 Register to R3

To access the RAMINDEX, write the CP15 register with:

MCR p15, 0, <Rt>, c15, c4, 0; Write RAM Index Register
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