4.3.58. Data L1 Data n Register

The DL1Datan, where n is from 0 to 3, characteristics are:

Purpose

Holds the data side L1 or L2 array information returned by the RAMINDEX write operation. See RAM Index Register for more information.

Note

Because the data, tag and TLB arrays are greater than 32-bits wide, the processor contains multiple DL1Data registers, to hold the array information.

Usage constraints

The DL1Datan is:

  • A read/write register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.14.

Figure 4.41 shows the DL1Datan bit assignments.

Figure 4.41. DL1Datan bit assignments

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Table 4.72 shows the DL1Datan bit assignments.

Table 4.72. DL1Datan bit assignments

BitsNameFunction
[31:0]Data

Holds the data side L1 or L2 array information


To access the DL1Datan, read or write the CP15 registers with:

MRC p15, 0, <Rt>, c15, c1, n; Read Data L1 Data n Register
MCR p15, 0, <Rt>, c15, c1, n; Write Data L1 Data n Register

where n is 0, 1, 2, or 3 for the Opcode_2 value of DL1Data0, DL1Data1, DL1Data2, or DL1Data3 Register.

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