4.3.40. Data Fault Status Register

The DFSR characteristics are:

Purpose

Holds status information about the last data fault.

Usage constraints

The DFSR is:

  • A read/write register.

  • Banked for Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.6.

There are two formats for this register. The current translation table format determines which format of the register is used. This section describes:

DFSR format when using the Short-descriptor translation table format

Figure 4.31 shows the DFSR bit assignments when using the Short-descriptor translation table format.

Figure 4.31. DFSR bit assignments for Short-descriptor translation table format

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Table 4.60 shows the DFSR bit assignments when using the Short-descriptor translation table format.

Table 4.60. DFSR bit assignments for Short-descriptor translation table format

BitsNameFunction
[31:14]-

Reserved, UNK/SBZP.

[13]CM

Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance operation generated the fault:

0

Abort not caused by a cache maintenance operation.

1

Abort caused by a cache maintenance operation.

On an asynchronous fault, this bit is unknown.

[12]ExT

External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:

0

External abort marked as DECERR.

1

External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

[11]WnR

Write not Read bit. This field indicates whether a write or a read access caused the abort:

0

Abort caused by a read access.

1

Abort caused by a write access.

For faults on CP15 cache maintenance operations, including the VA to PA translation operations, this bit always returns a value of 1.

[10]FS[4]Part of the Fault Status field. See bits[3:0] in this table.
[9]-

RAZ.

[8]-

Reserved, UNK/SBZP.

[7:4]Domain

The domain of the fault address. Specifies which of the 16 domains, D15-D0, was being accessed when a data fault occurred. ARMv7 deprecates any use of the domain field in the DFSR.

For a Permission fault that generates a Data Abort exception, this field is unknown.

[3:0]FS[3:0]

Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved:

b00001

Alignment fault.

b00100

Instruction cache maintenance fault[a].

b01100

Synchronous external abort on translation table walk, 1st level.

b01110

Synchronous external abort on translation table walk, 2nd level.

b11100

Synchronous parity error on translation table walk, 1st level.

b11110

Synchronous parity error on translation table walk, 2nd level.

b00101

Translation fault, 1st level.

b00111

Translation fault, 2nd level.

b00011

Access flag fault, 1st level.

b00110

Access flag fault, 2nd level.

b01001

Domain fault, 1st level.

b01011

Domain fault, 2nd level.

b01101

Permission fault, 1st level.

b01111

Permission fault, 2nd level.

b00010

Debug event.

b01000

Synchronous external abort, non-translation.

b11001

Synchronous parity error on memory access.

b10110

Asynchronous external abort.

b11000

Asynchronous parity error on memory access.

[a] This fault is not generated by the Cortex-A15 MPCore processor.


DFSR format when using the Long-descriptor translation table format

Figure 4.32 shows the DFSR bit assignments when using the Long-descriptor translation table format.

Figure 4.32. DFSR bit assignments for Long-descriptor translation table format

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Table 4.61 shows the DFSR bit assignments when using the Long-descriptor translation table format.

Table 4.61. DFSR bit assignments for Long-descriptor translation table format

BitsNameFunction
[31:14]-

Reserved, UNK/SBZP.

[13]CM

Cache maintenance fault. For synchronous faults, this bit indicates whether a cache maintenance operation generated the fault:

0

Abort not caused by a cache maintenance operation.

1

Abort caused by a cache maintenance operation.

On an asynchronous fault, this bit is unknown.

[12]ExT

External abort type. This field indicates whether an AXI Decode or Slave error caused an abort:

0

External abort marked as DECERR.

1

External abort marked as SLVERR.

For aborts other than external aborts this bit always returns 0.

[11]WnR

Write not Read bit. This field indicates whether a write or a read access caused the abort:

0

Abort caused by a read access.

1

Abort caused by a write access.

For faults on CP15 cache maintenance operations, including the VA to PA translation operations, this bit always returns a value of 1.

[10]-Reserved, UNK/SBZP.
[9]-

RAO.

[8:6]-

Reserved, UNK/SBZP.

[5:0]Status

Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved:

b0001LL

Translation fault, LL bits indicate level.

b0010LL

Access flag fault, LL bits indicate level.

b0011LL

Permission fault, LL bits indicate level.

b010000

Synchronous external abort.

b011000

Synchronous parity error on memory access.

b010001

Asynchronous external abort.

b011001

Asynchronous parity error on memory access.

b0101LL

Synchronous external abort on translation table walk, LL bits indicate level.

b0111LL

Synchronous parity error on memory access on translation table walk, LL bits indicate level.

b100001

Alignment fault.

b100010

Debug event.


Table 4.62 shows how the LL bits in the Status field encode the lookup level associated with the MMU fault.

Table 4.62. Encodings of LL bits associated with the MMU fault

LL bitsMeaning
00Reserved
01First level
10Second level
11Third level

To access the DFSR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c5, c0, 0; Read Data Fault Status Register
MCR p15, 0, <Rt>, c5, c0, 0; Write Data Fault Status Register
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