Cortex-A15 MPCore Technical Reference Manual: 4.3.41. Instruction Fault Status Register

4.3.41. Instruction Fault Status Register

The IFSR characteristics are:

Purpose

Holds status information about the last instruction fault.

Usage constraints

The IFSR is:

A read/write register.
Banked for Secure and Non-secure states.
Accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.6.

There are two formats for this register. The current translation table format determines which format of the register is used. This section describes:

IFSR format when using the Short-descriptor translation table format

Figure 4.33 shows the IFSR bit assignments when using the Short-descriptor translation table format.

Figure 4.33. IFSR bit assignments for Short-descriptor translation table format

Table 4.63 shows the IFSR bit assignments when using the Short-descriptor translation table format.

Table 4.63. IFSR bit assignments for Short-descriptor translation table format

Bits	Name	Function
[31:13]	-	Reserved, UNK/SBZP.
[12]	ExT	External abort type. This field indicates whether an AXI Decode or Slave error caused an abort: 0 External abort marked as DECERR. 1 External abort marked as SLVERR. For aborts other than external aborts this bit always returns 0.
[11]	-	Reserved, UNK/SBZP.
[10]	FS[4]	Part of the Fault Status field. See bits[3:0] in this table.
[9]	-	RAZ.
[8:4]	-	Reserved, UNK/SBZP.
[3:0]	FS[3:0]	Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved: `b01100` Synchronous external abort on translation table walk, 1st level. `b01110` Synchronous external abort on translation table walk, 2nd level. `b11100` Synchronous parity error on translation table walk, 1st level. `b11110` Synchronous parity error on translation table walk, 2nd level. `b00101` Translation fault, 1st level. `b00111` Translation fault, 2nd level. `b00011` Access flag fault, 1st level. `b00110` Access flag fault, 2nd level. `b01001` Domain fault, 1st level. `b01011` Domain fault, 2nd level. `b01101` Permission fault, 1st level. `b01111` Permission fault, 2nd level. `b00010` Debug event. `b01000` Synchronous external abort, non-translation. `b11001` Synchronous parity error on memory access.

IFSR format when using the Long-descriptor translation table format

Figure 4.34 shows the IFSR bit assignments when using the Long-descriptor translation table format.

Figure 4.34. IFSR bit assignments for Long-descriptor translation table format

Table 4.64 shows the IFSR bit assignments when using the Long-descriptor translation table format.

Table 4.64. IFSR bit assignments for Long-descriptor translation table format

Bits	Name	Function
[31:13]	-	Reserved, UNK/SBZP.
[12]	ExT	External abort type. This field indicates whether an AXI Decode or Slave error caused an abort: 0 External abort marked as DECERR. 1 External abort marked as SLVERR. For aborts other than external aborts this bit always returns 0.
[11:10]	-	Reserved, UNK/SBZP.
[9]	-	RAO.
[8:6]	-	Reserved, UNK/SBZP.
[5:0]	Status	Fault Status bits. This field indicates the type of exception generated. Any encoding not listed is reserved: `b0001LL` Translation fault, LL bits indicate level. `b0010LL` Access flag fault, LL bits indicate level. `b0011LL` Permission fault, LL bits indicate level. `b010000` Synchronous external abort. `b011000` Synchronous parity error on memory access. `b0101LL` Synchronous external abort on translation table walk, LL bits indicate level. `b0111LL` Synchronous parity error on memory access on translation table walk, LL bits indicate level. `b100010` Debug event.

Table 4.65 shows how the LL bits in the Status field encode the lookup level associated with the MMU fault.

Table 4.65. Encodings of LL bits associated with the MMU fault

LL Bits	Meaning
00	Reserved
01	First level
10	Second level
11	Third level

Note

If a Data Abort exception is generated by an instruction cache maintenance operation, the fault is reported as a Cache Maintenance fault in the DFSR or HSR with the appropriate Fault Status code. For such exceptions reported in the DFSR, the corresponding IFSR is unknown.

To access the IFSR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c5, c0, 1; Read Instruction Fault Status Register

MCR p15, 0, <Rt>, c5, c0, 1; Write Instruction Fault Status Register

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