Cortex-A15 MPCore Technical Reference Manual: 4.3.9. Debug Feature Register 0

The ID_DFR0 characteristics are:

Purpose

Provides top-level information about the debug system.

Usage constraints

The ID_DFR0 is:

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.8 shows the ID_DFR0 bit assignments.

Figure 4.8. ID_DFR0 bit assignments

Table 4.36 shows the ID_DFR0 bit assignments.

Table 4.36. ID_DFR0 bit assignments

Bits	Name	Function
[31:28]	-	Reserved, RAZ.
[27:24]	Performance Monitors Extension	Indicates support for coprocessor-based ARM Performance Monitors Extension: `0x2` Processor supports Performance Monitors Extension, PMUv2 architecture.
[23:20]	Debug model, M profile	Indicates support for memory-mapped debug model for M profile processors: `0x0` Processor does not support M profile Debug architecture, with memory-mapped access.
[19:16]	Memory-mapped trace model	Indicates support for memory-mapped trace model: `0x1` Processor supports ARM trace architecture, with memory-mapped access.
[15:12]	Coprocessor trace model	Indicates support for coprocessor-based trace model: `0x0` Processor does not support ARM trace architecture, with CP14 access.
[11:8]	Memory-mapped debug model	Indicates support for memory-mapped debug model: `0x5` Processor supports v7.1 Debug architecture, with memory-mapped access.
[7:4]	Coprocessor Secure debug model	Indicates support for coprocessor-based Secure debug model: `0x5` Processor supports v7.1 Debug architecture, with CP14 access.
[3:0]	Coprocessor debug model	Indicates support for coprocessor-based debug model: `0x5` Processor supports v7.1 Debug architecture, with CP14 access.

To access the ID_DFR0, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 2; Read Debug Feature Register 0

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