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Home > System Control > Register descriptions > Debug Feature Register 0 |
The ID_DFR0 characteristics are:
Provides top-level information about the debug system.
The ID_DFR0 is:
A read-only register.
Common to the Secure and Non-secure states.
Only accessible from PL1 or higher.
Available in all configurations.
See the register summary in Table 4.2.
Figure 4.8 shows the ID_DFR0 bit assignments.
Table 4.36 shows the ID_DFR0 bit assignments.
Table 4.36. ID_DFR0 bit assignments
Bits | Name | Function |
---|---|---|
[31:28] | - | Reserved, RAZ. |
[27:24] | Performance Monitors Extension | Indicates support for coprocessor-based ARM Performance Monitors Extension:
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[23:20] | Debug model, M profile | Indicates support for memory-mapped debug model for M profile processors:
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[19:16] | Memory-mapped trace model | Indicates support for memory-mapped trace model:
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[15:12] | Coprocessor trace model | Indicates support for coprocessor-based trace model:
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[11:8] | Memory-mapped debug model | Indicates support for memory-mapped debug model:
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[7:4] | Coprocessor Secure debug model | Indicates support for coprocessor-based Secure debug model:
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[3:0] | Coprocessor debug model | Indicates support for coprocessor-based debug model:
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To access the ID_DFR0, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c1, 2; Read Debug Feature Register 0