7.7.4. Distributed virtual memory transactions

In a system where the Cortex-A15 MPCore processor can receive a Distributed Virtual Memory (DVM) synchronization message over the AXI master snoop address channel, BRESP for any write transaction must not be asserted to the processor until all AXI masters that might have initiated the DVM synchronization request observe the transaction.


The Cortex-A15 MPCore processor does not support a multi-part DVM hint message.

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