A.2. Clock signals

Table A.1 shows the clock and clock enable signals.

Table A.1. Clock and clock enable signals

SignalTypeDescription
CLKInput

Global clock.

CLKEN

Input

Global clock enable. This signal can only be deasserted with all the processors in the MPCore device and L2 are in WFI mode, and both the ACE and ACP are idle.

CPUCLKOFF[N:0][a]

Input

Individual processor clock disable.

0

Processor clock is enabled.

1

Processor clock is stopped.

This signal is only present if the Cortex-A15 MPCore processor is configured with the CPUCLKOFF pins. The default configuration does not include the CPUCLKOFF pins. This signal can only be asserted when the processor is already powered off, or when the processor is powered up. To enable the powerup reset sequence to complete, this signal must be deasserted after power has been completely restored. See Clocks for more information.

[a] These signals are not available in revisions prior to r3p0.


See Clocking and resets for more information.

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