6.4.5. Synchronization primitives

The L1 memory system supports the ARMv7-A Load-Exclusive, Store-Exclusive, and Clear-Exclusive synchronization primitive instructions. For all nonshareable memory pages, the synchronization primitives are supported with a local monitor that is in each L1 memory system. For shareable memory pages, the local monitor is used in conjunction with a global monitor. Where the global monitor resides depends on the memory type and cacheability.

Internal coherent global monitor

If synchronization primitives are used for memory pages that are shareable Normal Write-Back and the cache is enabled, SCTLR.C is 1, the external monitor on AXI is not used. Instead, the global monitor function is handled in the L1 and L2 memory system using the cache coherence information.

External global monitor

If synchronization primitives are used for memory pages that are Strongly-ordered, Device, or Inner-Shareable Normal Non-Cacheable, a global monitor must be provided in the interconnect. See the ARM Architecture Reference Manual for more information. The memory requests are sent on the AXI interface as Read-Exclusive or Write-Exclusive. See the AMBA AXI Protocol Specification for more information.

Note

  • Use of synchronization primitives on addresses in regions marked as Strongly-ordered or Device is unpredictable in the ARMv7-A Architecture. Code that makes such accesses is not portable.

  • Load-Exclusive and Store-Exclusive requests are not supported to shareable Normal Write-Through memory.

  • Load-Exclusive and Store-Exclusive requests are not supported to shareable Normal Write-Back memory if the cache is disabled, SCTLR.C is 0.

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