7.8.1. Burst support

ACP supports a maximum burst lengths of 16 over AXI3. The L2 memory system breaks up transactions on a cache line boundary, creating additional requests to the L2 pipeline, and possibly the ACE for L2 cache misses. Ordering is maintained for the requests, and the responses are generated in the appropriate order on the ACP. For reads, data must be returned in the order of the original burst received. For writes to Strongly-ordered memory, the BRESP is generated from the final destination. All other BRESPs are generated on the last write data packet received on the ACP interface.

The Cortex-A15 MPCore processor supports fixed burst type transactions only to Device and Strongly-ordered memory.

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