4.3.28. Auxiliary Control Register

The ACTLR characteristics are:

Purpose

Provides configuration and control options for the processor.

Usage constraints

The ACTLR:

  • Is a read/write register.

  • Common to the Secure and Non-secure states.

  • Is only accessible from PL1 or higher, with access rights that depend on the mode:

    • Read/write in Secure PL1 modes.

    • Read-only and write-ignored in Non-secure PL1 and PL2 modes if NSACR.NS_SMP is 0.

    • Read/write in Non-secure PL1 and PL2 modes if NSACR.NS_SMP is 1. In this case, all bits are write-ignored except for the SMP bit.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.24 shows the ACTLR bit assignments.

Figure 4.24. ACTLR bit assignments

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Table 4.53 shows the ACTLR bit assignments.

Table 4.53. ACTLR bit assignments

BitsNameFunction
[31]Snoop-delayed exclusive handling

Snoop-delayed exclusive handling:

0

Normal exclusive handling behavior. This is the reset value.

1

Modifies exclusive handling behavior by delaying certain snoop requests.

[30]Force main clock enable active

Forces main processor clock enable active:

0

Does not prevent the clock generator from stopping the processor clock. This is the reset value.

1

Prevents the clock generator from stopping the processor clock.

[29]Force NEON/VFP clock enable active

Forces NEON and VFP unit clock enable active:

0

Does not prevent the clock generator from stopping the NEON and VFP unit clock. This is the reset value.

1

Prevents the clock generator from stopping the NEON and VFP unit clock.

[28:27]Write streaming no-allocate threshold

Write streaming no-allocate threshold:

b00

12th consecutive streaming cache line does not allocate in the L1 or L2 cache. This is the reset value.

b01

128th consecutive streaming cache line does not allocate in the L1 or L2 cache.

b10

512th consecutive streaming cache line does not allocate in the L1 or L2 cache.

b11

Disables streaming. All write-allocate lines allocate in the L1 or L2 cache.

[26:25]Write streaming no L1-allocate threshold

Write streaming no L1-allocate threshold:

b00

4th consecutive streaming cache line does not allocate in the L1 cache. This is the reset value.

b01

64th consecutive streaming cache line does not allocate in the L1 cache.

b10

128th consecutive streaming cache line does not allocate in the L1 cache.

b11

Disables streaming. All write-allocate lines allocate in the L1 cache.

[24]Non-cacheable streaming enhancement

Non-cacheable streaming enhancement:

0

Disables higher performance Non-Cacheable, Write-Back, or Write-Through load forwarding. This is the reset value.

1

Enables higher performance Non-Cacheable, Write-Back, or Write-Through load forwarding. See Non-cacheable streaming enhancement for more information.

[23]Force in-order requests to the same set and way

Forces in-order requests to the same set and way:

0

Does not force in-order requests to the same set and way. This is the reset value.

1

Forces in-order requests to the same set and way.

[22]Force in-order load issue

Force in-order load issue:

0

Does not force in-order load issue. This is the reset value.

1

Forces in-order load issue.

[21]Disable L2 TLB prefetching

Disables L2 TLB prefetching:

0

Enables L2 TLB prefetching. This is the reset value.

1

Disables L2 TLB prefetching.

[20]Disable L2 translation table walk IPA PA cache

Disables L2 translation table walk Intermediate Physical Address (IPA) to Physical Address (PA) cache:

0

Enables L2 translation table walk IPA to PA cache. This is the reset value.

1

Disables L2 translation table walk IPA to PA cache.

[19]Disable L2 stage 1 translation table walk cache

Disables L2 stage 1 translation table walk cache:

0

Enables L2 stage 1 translation table walk cache. This is the reset value.

1

Disables L2 stage 1 translation table walk cache.

[18]Disable L2 stage 1 translation table walk L2 PA cache

Disables L2 stage 1 translation table walk L2 PA cache:

0

Enables L2 stage 1 translation table walk L2 PA cache. This is the reset value.

1

Disables L2 stage 1 translation table walk L2 PA cache.

[17]Disable L2 TLB performance optimization

Disables L2 TLB performance optimization:

0

Enables L2 TLB optimization. This is the reset value.

1

Disables L2 TLB optimization.

[16]Enable full Strongly-ordered and Device load replay

Enables full Strongly-ordered and Device load replay:

0

Disables full Strongly-ordered and Device load replay. This is the reset value.

1

Enables full Strongly-ordered and Device load replay.

[15]Force in-order issue in branch execution unit

Forces in-order issue in branch execution unit:

0

Disables forced in-order issue. This is the reset value.

1

Forces in-order issue.

[14]Force limit of one instruction group commit/de-allocate per cycle

Forces limit of one instruction group to commit and de-allocate per cycle:

0

Normal commit and de-allocate behavior. This is the reset value.

1

Limits commit and de-allocate to one instruction group per cycle.

[13]Flush after CP14, CP15 writes

Flushes after certain CP14 and CP15 writes:

0

Normal behavior for CP14 and CP15 writes. This is the reset value.

1

Flushes after certain CP14 and CP15 writes.

[12]Force push of CP14 and CP15 registers

Forces push of certain CP14 and CP15 registers from local dispatch copies to shadow copies:

0

Normal behavior for CP14 and CP15 instructions. This is the reset value.

1

Pushes certain CP14 and CP15 registers from local dispatch copies to shadow copies.

Note

Setting this bit to 1 forces the processor to behave as if bit[13] is set to 1.

[11]Limit to one instruction per instruction group

Limits to one instruction per instruction group:

0

Normal instruction grouping. This is the reset value.

1

Limits to one instruction per instruction group.

[10]Force serialization after each instruction group

Forces serialization after each instruction group:

0

Disables forced serialization after each instruction group. This is the reset value.

1

Forces serialization after each instruction group.

Note

Setting this bit to 1 forces the processor to behave as if bit[11] is set to 1.

[9]Disable flag renaming optimization

Disables flag renaming optimization:

0

Enables normal flag renaming optimization. This is the reset value.

1

Disables normal flag renaming optimization.

[8]Execute WFI instruction as a NOP instruction

Executes WFI instruction as a NOP instruction:

0

Executes WFI instruction as defined in the ARM Architecture Reference Manual. This is the reset value.

1

Executes WFI instruction as a NOP instruction, and does not put the processor in low-power state.

[7]Execute WFE instruction as a NOP instruction

Executes WFE instruction as a NOP instruction:

0

Executes WFE instruction as defined in the ARM Architecture Reference Manual. This is the reset value.

1

Executes WFE instruction as a NOP instruction, and does not put the processor in low-power state.

[6]SMP

Enables the processor to receive instruction cache, BTB, and TLB maintenance operations from other processors. Clearing the SMP bit disables the processor from receiving the instruction cache, BTB, and TLB maintenance operations from other processors and is a required step when powering down the processor:

0

Disables receiving of instruction cache, BTB, and TLB maintenance operations. This is the reset value.

1

Enables receiving of instruction cache, BTB, and TLB maintenance operations.

Note

  • Any processor instruction cache, BTB, and TLB maintenance operations can execute the request, regardless of the value of the SMP bit.

  • This bit has no impact on data cache maintenance operations.

  • In the Cortex-A15 MPCore processor, the L1 data cache and L2 cache are always coherent, for shared or non-shared data, regardless of the value of the SMP bit.

  • You must set this bit before enabling the caches and MMU, or performing any cache and TLB maintenance operations. You must clear this bit during a processor powerdown sequence. See Power management.

[5]Execute PLD instructions as a NOP

Execute PLD and PLDW instructions as a NOP instruction:

0

Executes PLD and PLDW instructions as defined in the ARM Architecture Reference Manual. This is the reset value.

1

Executes PLD and PLDW instructions as a NOP instruction.

[4]Disable indirect predictor

Disables indirect predictor:

0

Enables indirect predictor. This is the reset value.

1

Disables indirect predictor.

[3]Disable micro-BTB

Disables micro-Branch Target Buffer (BTB):

0

Enables micro-BTB. This is the reset value.

1

Disables micro-BTB.

[2]Limit to one loop buffer detect per flush

Limits to one loop buffer detect per flush:

0

Normal behavior. This is the reset value.

1

Limits to one loop buffer detect per flush.

[1]Disable loop buffer

Disables loop buffer:

0

Enables loop buffer. This is the reset value.

1

Disables loop buffer.

[0]Enable invalidates of BTB

Enables invalidate of BTB:

0

The CP15 Invalidate Instruction Cache All and Invalidate Instruction Cache by MVA instructions only invalidates the instruction cache array. This is the reset value.

1

The CP15 Invalidate Instruction Cache All and Invalidate Instruction Cache by MVA instructions invalidates the instruction cache array and branch target buffer.


To access the ACTLR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c0, 1 ; Read Auxiliary Control Register
MCR p15, 0, <Rt>, c1, c0, 1 ; Write Auxiliary Control Register
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