A.3. Reset signals

Table A.2 shows the reset and reset control signals. The value of N is one less than the number of processors in your design.

Table A.2. Reset signals

SignalTypeDescription
nCPUPORESET[N:0]Input

Individual processor resets:

0

Apply reset to processor that includes NEON and VFP, Debug, PTM, breakpoint and watchpoint logic.

1

Do not apply reset to processor that includes NEON and VFP, Debug, PTM, breakpoint and watchpoint logic.

nCORERESET[N:0]Input

Individual processor reset excluding Debug and PTM:

0

Apply reset to processor that includes NEON and VFP, but excludes Debug, PTM, breakpoint and watchpoint logic.

1

Do not apply reset to processor that includes NEON and VFP, but excludes Debug, PTM, breakpoint and watchpoint logic.

nCXRESET[N:0]Input

Individual processor NEON and VFP resets:

0

Apply reset to NEON and VFP.

1

Do not apply reset to NEON and VFP.

nDBGRESET[N:0]Input

Individual processor Debug and PTM resets:

0

Apply reset to Debug, PTM, breakpoint and watchpoint logic.

1

Do not apply reset to Debug, PTM, breakpoint and watchpoint logic.

nL2RESETInput

L2 reset:

0

Apply reset to shared L2 memory system controller.

1

Do not apply reset to shared L2 memory system controller.

L2RSTDISABLEInput

L2 cache hardware reset disable:

0

L2 cache is reset by hardware.

1

L2 cache is not reset by hardware.


See Clocking and resets for more information.

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