4.2. Register summary

This section gives a summary of the CP15 system control registers. For more information on using the CP15 system control registers, see the ARM Architecture Reference Manual.

The system control coprocessor is a set of registers that you can write to and read from. Some of the registers permit more than one type of operation.

The following subsections describe the CP15 system control registers grouped by CRn order, and accessed by the MCR and MRC instructions in the order of CRn, Op1, CRm, Op2:

The Cortex-A15 MPCore processor supports the Virtualization Extensions (VE), the Large Physical Address Extension (LPAE), and the Generic Timer. See Virtualization Extensions architecture, Large Physical Address Extension architecture, and Chapter 9 Generic Timer for more information. The VE, LPAE, and Generic Timer contain a number of 64-bit registers. The following subsection describes these registers and provides cross references to individual register descriptions:

In addition to listing the CP15 system control registers by CRn ordering, the following subsections describe the CP15 system control registers by functional group:

Table 4.1 describes the column headings that the CP15 register summary tables use throughout this chapter.

Table 4.1. Column headings definition for CP15 register summary tables

Column nameDescription
CRnRegister number within the system control coprocessor
Op1Opcode_1 value for the register
CRmOperational register number within CRn
Op2Opcode_2 value for the register
NameShort form architectural, operation, or code name for the register
ResetReset value of register
DescriptionCross-reference to register description

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