4.3.5. Multiprocessor Affinity Register

The MPIDR characteristics are:


Provides an additional processor identification mechanism for scheduling purposes in a multiprocessor system.

Usage constraints

The MPIDR is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.


Available in all configurations.


See the register summary in Table 4.2.

Figure 4.4 shows the MPIDR bit assignments.

Figure 4.4. MPIDR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 4.32 shows the MPIDR bit assignments.

Table 4.32. MPIDR bit assignments


RAO. Indicates that the processor implements the Multiprocessing Extensions register format.


Indicates a Uniprocessor system, as distinct from processor 0 in a multiprocessor system:


Processor is part of a multiprocessor system.

[29:25]-Reserved, RAZ.

Indicates whether the lowest level of affinity consists of logical processors that are implemented using a hardware multi-threading type approach:


Performance of processors at the lowest affinity level is largely independent.


Reserved, RAZ.

[11:8]Cluster ID

Indicates the value read in the CLUSTERID configuration pin. It identifies a processor in a multiprocessor configuration.


Reserved, RAZ.

[1:0]CPU ID

Indicates the processor number in a Cortex-A15 MPCore device. For:

  • One processor, the CPU ID is 0x0.

  • Two processors, the CPU IDs are 0x0 and 0x1.

  • Three processors, the CPU IDs are 0x0, 0x1, and 0x2.

  • Four processors, the CPU IDs are 0x0, 0x1, 0x2, and 0x3.

To access the MPIDR, read the CP15 registers with:

MRC p15, 0, <Rt>, c0, c0, 5; Read Multiprocessor Affinity Register
Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G