4.3.22. Cache Level ID Register

The CLIDR characteristics are:

Purpose

Identifies:

  • The type of cache, or caches, implemented at each level, up to a maximum of seven levels.

  • The Level of Coherency and Level of Unification for the cache hierarchy.

Usage constraints

The CLIDR is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.19 shows the CLIDR bit assignments.

Figure 4.19. CLIDR bit assignments

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Table 4.48 shows the CLIDR bit assignments.

Table 4.48. CLIDR bit assignments

BitsNameFunction
[31:30]-

Reserved, RAZ.

[29:27]]LoUU

Indicates the Level of Unification Uniprocessor for the cache hierarchy:

b001

L2 cache.

[26:24]LoC

Indicates the Level of Coherency for the cache hierarchy:

b010

L3 cache.

[23:21]LoUIS

Indicates the Level of Unification Inner Shareable for the cache hierarchy:

b001

L2 cache.

[20:18]Ctype7

Indicates the type of cache implemented at level 7:

b000

No cache.

[17:15]Ctype6

Indicates the type of cache implemented at level 6:

b000

No cache.

[14:12]Ctype5

Indicates the type of cache implemented at level 5:

b000

No cache.

[11:9]Ctype4

Indicates the type of cache implemented at level 4:

b000

No cache.

[8:6]Ctype3

Indicates the type of cache implemented at level 3:

b000

No cache.

[5:3]Ctype2

Indicates the type of cache implemented at level 2:

b100

Unified cache.

[2:0]Ctype1

Indicates the type of cache implemented at level 1:

b011

Separate instruction and data caches.


To access the CLIDR, read the CP15 register with:

MRC p15, 1, <Rt>, c0, c0, 1 ; Read Cache Level ID Register
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