6.4.3. Cache disabled behavior

When you clear the C bit in the CP15 System Control Register for a given processor, see System Control Register, data caching is disabled and no new cache lines are allocated to the L1 data cache and L2 cache because of requests from that processor. This is important when cleaning and invalidating the caches for power down. Cache lines can be allocated from memory requests of other processors, unless their cache enable bits are also cleared. The effect on the L1 memory system is that all Write-Back Read-Write-Allocate pages are treated as Write-Back No-Allocate pages.

When you disable the cache, all Write-Back Cacheable requests still look up the L1 cache. If there is a cache hit, the cache is read or updated in the same way as if the cache is enabled. This enables Cacheable memory to remain fully coherent while the cache is disabled.

While the cache is disabled, it remains fully coherent with the L2 cache and the other L1 data caches.

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