4.3.60. L2 Auxiliary Control Register

The L2ACTLR characteristics are:

Purpose

Provides configuration and control options for the L2 memory system.

Usage constraints

The L2ACTLR:

  • Is a read/write register.

  • Is Common to the Secure and Non-secure states.

  • Is only accessible from PL1 or higher, with access rights that depend on the mode:

    • Read/write in Secure PL1 modes.

    • Read-only and write-ignored in Non-secure PL1 and PL2 modes.

  • This register can only be written when the L2 memory system is idle. ARM recommends that you write to this register after a powerup reset before the MMU is enabled and before any ACE or ACP traffic has begun.

    If the register must be modified after a powerup reset sequence, to idle the L2 memory system, you must take the following steps:

    1. Disable the MMU from each processor followed by an ISB to ensure the MMU disable operation is complete, then followed by a DSB to drain previous memory transactions.

    2. Ensure that the system has no outstanding AC channel coherence requests to the Cortex-A15 MPCore processor.

    3. Ensure that the system has no outstanding ACP requests to the Cortex-A15 MPCore processor.

When the L2 is idle, the processor can update the L2ACTLR followed by an ISB. After the L2ACTLR is updated, the MMUs can be enabled and normal ACE and ACP traffic can resume.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.14.

Figure 4.59 shows the L2ACTLR bit assignments.

Figure 4.59. L2ACTLR bit assignments

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Table 4.74 shows the L2ACTLR bit assignments.

Table 4.74. L2ACTLR bit assignments

BitsNameFunction
[31:29]-

Reserved, RAZ/WI.

[28]Force L2 tag bank clock enable active

Forces L2 tag bank clock enable active:

0

Does not prevent the clock generator from stopping the L2 tag bank clock. This is the reset value.

1

Prevents the clock generator from stopping the L2 tag bank clock.

This bit applies to each of the four L2 cache tag bank clocks.

[27]Force L2 logic clock enable active

Forces L2 logic clock enable active:

0

Does not prevent the clock generator from stopping the L2 logic clock. This is the reset value.

1

Prevents the clock generator from stopping the L2 logic clock.

[26]Enable L2, GIC, and Timer regional clock gates[a]

Enables L2, GIC, and Timer regional clock gates:

0

Disables the L2, GIC, and Timer regional clock gates. This is the reset value.

1

Enables the L2, GIC, and Timer regional clock gates for additional clock gating. When this bit is set, the regional clock gates can gate-off the clock and potentially reduce dynamic power dissipation.

[25:17]-

Reserved, RAZ/WI.

[16]Enable replay threshold single issue[a]

Enables replay threshold single issue:

0

Disables replay threshold single issue. This is the reset value.

1

Enables replay threshold single issue. If 32 consecutive transactions on a tag bank replay, then single issue is forced until a transaction successfully passes hazard checking.

[15]Enable CPU WFI retention mode[a]

Enables CPU WFI retention mode:

0

Disables CPU WFI retention mode. This is the reset value.

1

Enables CPU WFI retention mode.

[14]Enable UniqueClean evictions with data[a]

Enables UniqueClean evictions with data:

0

Disables UniqueClean evictions with data. This is the reset value.

1

Enables UniqueClean evictions with data.

[13]Disable SharedClean data transfers[a]

Disables SharedClean data transfers:

0

Enables SharedClean data transfers. This is the reset value.

1

Disables SharedClean data transfers.

[12]Disable multiple outstanding WriteClean/WriteBack/Evicts using the same AWID[a]

Disables multiple outstanding WriteClean/WriteBack/Evicts using the same AWID:

0

Enables multiple outstanding WriteClean/WriteBack/Evicts using the same AWID. This is the reset value.

1

Disables multiple outstanding WriteClean/WriteBack/Evicts using the same AWID.

[11]Disable Data Synchronization Barrier (DSB) with no Distributed Virtual Memory (DVM) synchronization[a]

Disables DSB with no DVM synchronization:

0

Enables DSB with no DVM synchronization. This is the reset value.

1

Disables DSB with no DVM synchronization.

[10]Disable non-secure debug array read

Disables non-secure debug array read:

0

Enables non-secure debug array read access to non-secure memory. This is the reset value.

1

Disables non-secure debug array read access.

[9]Enable use of PF bit in L2 cache replacement algorithm

Enable use of Prefetch bit in L2 cache replacement algorithm:

0

Disables use of Prefetch bit in L2 cache replacement algorithm. This is the reset value.

1

Enables use of Prefetch bit in L2 cache replacement algorithm.

[8]Disable DVM/CMO message broadcast

Disables Distributed Virtual Memory (DVM) transactions and cache maintenance operation message broadcast:

0

Enables DVM and cache maintenance operation message broadcast. This is the reset value.

1

Disables DVM and cache maintenance operation message broadcast.

[7]Enable hazard detect timeout

Enables hazard detect timeout:

0

Disables hazard detect timeout. This is the reset value.

1

Enables hazard detect timeout.

[6]Disable shareable transactions from master

Disables shareable transactions from master:

0

Enables shareable transactions from master. This is the reset value.

1

Disables shareable transactions from master.

[5]-

Reserved, RAZ/WI.

[4]Disable WriteUnique and WriteLineUnique transactions from master

Disables WriteUnique and WriteLineUnique transactions from master:

0

Enables WriteUnique and WriteLineUnique transactions from master. This is the reset value.

1

Disables WriteUnique and WriteLineUnique transactions from master.

[3]Disable clean/evict push to external

Disables clean/evict push to external:

0

Enables clean/evict to be pushed out to external. This is the reset value.

1

Disables clean/evict from being pushed to external.

[2]Limit to one request per tag bank

Limit to one request per tag bank:

0

Normal behavior of permitting parallel requests to the tag banks. This is the reset value.

1

Limits to one request per tag bank.

[1]Enable arbitration replay threshold timeout

Enable arbitration replay threshold timeout:

0

Disables arbitration replay threshold timeout. This is the reset value.

1

Enables arbitration replay threshold timeout.

[0]Disable prefetch forwarding

Disables prefetch forwarding:

0

Enables prefetch forwarding. This is the reset value.

1

Disables prefetch forwarding.

[a] This bit is not available in revisions prior to r3p0.


To access the L2ACTLR, read or write the CP15 register with:

MRC p15, 1, <Rt>, c15, c0, 0; Read L2 Auxiliary Control Register
MCR p15, 1, <Rt>, c15, c0, 0; Write L2 Auxiliary Control Register
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