7.7.3. ACE transfers

For Normal Inner-Cacheable memory transfers initiated from one of the Cortex-A15 MPCore processors, the following transfers are supported on the ACE:

For Non-Cacheable, Cacheable but not allocated, Strongly-ordered, or Device transactions initiated from one of the Cortex-A15 MPCore processors, the following transfers are supported on the ACE:

If there are requests on the Cortex-A15 MPCore ACP port, the following transfers can be generated on the ACE if comparable requests are received on the ACP:

Note

  • ACP requests with burst mode INCR that crosses a 64-byte aligned boundary are broken into multiple ACE requests of burst type INCR and of size 64 bytes or less.

  • ACP requests with burst mode WRAP that crosses a 64-byte aligned boundary are broken into multiple ACE requests of burst type INCR of size 64 bytes or less. The received data is returned on the ACP port in the order required by the WRAP request.

  • ACP requests with burst mode FIXED that requests more than 64 bytes generate multiple FIXED requests on the ACE of size 64 bytes or less.

Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G
Non-ConfidentialID080412