Cortex-A15 MPCore Technical Reference ManualRevision: r3p2
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4.3.14. Memory Model Feature Register 3

The ID_MMFR3 characteristics are:

Purpose

Provides information about the implemented memory model and memory management support of the processor.

Usage constraints

The ID_MMFR3 is:

  • A read-only register.

  • Common to the Secure and Non-secure states.

  • Only accessible from PL1 or higher.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.12 shows the ID_MMFR3 bit assignments.

Figure 4.12. ID_MMFR3 bit assignments

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Table 4.40 shows the ID_MMFR3 bit assignments.

Table 4.40. ID_MMFR3 bit assignments

BitsNameFunction
[31:28]Supersection support

Indicates support for supersections:

0x0

Processor supports supersections.

[27:24]Cached memory size

Indicates the physical memory size supported by the processor caches:

0x2

Processor caches support 40-bit physical address range.

[23:20]Coherent walk

Indicates whether translation table updates require a clean to the point of unification:

0x1

Updates to the translation tables do not require a clean to the point of unification to ensure visibility by subsequent translation table walks.

[19:16]-

Reserved, RAZ.

[15:12]Maintenance broadcast

Indicates whether cache, TLB and branch predictor operations are broadcast:

0x2

Cache, TLB and branch predictor operations affect structures according to shareability and defined behavior of instructions.

[11:8]Branch predictor maintenance

Indicates the supported branch predictor maintenance operations.

0x2

Processor supports:

  • Invalidate all branch predictors.

  • Invalidate branch predictors by MVA.

[7:4]Cache maintenance by set/way

Indicates the supported cache maintenance operations by set/way.

0x1

Processor supports:

  • Invalidate data cache by set/way.

  • Clean data cache by set/way.

  • Clean and invalidate data cache by set/way.

[3:0]Cache maintenance by MVA

Indicates the supported cache maintenance operations by MVA.

0x1

Processor supports:

  • Invalidate data cache by MVA.

  • Clean data cache by MVA.

  • Clean and invalidate data cache by MVA.

  • Invalidate instruction cache by MVA.

  • Invalidate all instruction cache entries.


To access the ID_MMFR3, read the CP15 register with:

MRC p15, 0, <Rt>, c0, c1, 7; Read Memory Model Feature Register 3
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