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Home > System Control > Register descriptions > Memory Model Feature Register 3 |
The ID_MMFR3 characteristics are:
Provides information about the implemented memory model and memory management support of the processor.
The ID_MMFR3 is:
A read-only register.
Common to the Secure and Non-secure states.
Only accessible from PL1 or higher.
Available in all configurations.
See the register summary in Table 4.2.
Figure 4.12 shows the ID_MMFR3 bit assignments.
Table 4.40 shows the ID_MMFR3 bit assignments.
Table 4.40. ID_MMFR3 bit assignments
Bits | Name | Function |
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[31:28] | Supersection support | Indicates support for supersections:
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[27:24] | Cached memory size | Indicates the physical memory size supported by the processor caches:
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[23:20] | Coherent walk | Indicates whether translation table updates require a clean to the point of unification:
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[19:16] | - | Reserved, RAZ. |
[15:12] | Maintenance broadcast | Indicates whether cache, TLB and branch predictor operations are broadcast:
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[11:8] | Branch predictor maintenance | Indicates the supported branch predictor maintenance operations.
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[7:4] | Cache maintenance by set/way | Indicates the supported cache maintenance operations by set/way.
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[3:0] | Cache maintenance by MVA | Indicates the supported cache maintenance operations by MVA.
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To access the ID_MMFR3, read the CP15 register with:
MRC p15, 0, <Rt>, c0, c1, 7; Read Memory Model Feature Register 3