9.3. Generic Timer programmers model

Within each processor, a set of Generic Timer registers are allocated to the CP15 coprocessor space. The Generic Timer registers are either 32-bits wide or 64-bits wide.

Table 9.2 shows the Generic Timer registers.

Table 9.2. Generic Timer registers

NameCRnOp1CRmOp2ResetWidthDescription
CNTFRQc140c00UNK32-bit

Counter Frequency Register, see the ARM Architecture Reference Manual

CNTPCT-0c14-UNK64-bit

Physical Count Register, see the ARM Architecture Reference Manual

CNTKCTLc140c10-[a]32-bit

Timer PL1 Control Register, see the ARM Architecture Reference Manual

CNTP_TVAL  c20UNK32-bit

PL1 Physical TimerValue Register, see the ARM Architecture Reference Manual

CNTP_CTL   1

-[b]

32-bit

PL1 Physical Timer Control Register, see the ARM Architecture Reference Manual

CNTV_TVAL  c30UNK32-bit

Virtual TimerValue Register, see the ARM Architecture Reference Manual

CNTV_CTL   1[b]32-bit

Virtual Timer Control Register, see the ARM Architecture Reference Manual

CNTVCT-1c14-UNK64-bit

Virtual Count Register, see the ARM Architecture Reference Manual

CNTP_CVAL 2  UNK64-bit

PL1 Physical Timer CompareValue Register, see the ARM Architecture Reference Manual

CNTV_CVAL 3  UNK64-bit

Virtual Timer CompareValue Register, see the ARM Architecture Reference Manual

CNTVOFF 4  UNK64-bit

Virtual Offset Register, see the ARM Architecture Reference Manual

CNTHCTLc144c10

-[c]

32-bit

Timer PL2 Control Register, see the ARM Architecture Reference Manual

CNTHP_TVAL  c20UNK32-bit

PL2 Physical TimerValue Register, see the ARM Architecture Reference Manual

CNTHP_CTL   1[b]32-bit

PL2 Physical Timer Control Register, see the ARM Architecture Reference Manual

CNTHP_CVAL-6c14-UNK64-bit

PL2 Physical Timer CompareValue Register, see the ARM Architecture Reference Manual

[a] The reset value for bits[9:8, 2:0] is b00000.

[b] The reset value for bit[0] is 0.

[c] The reset value for bit[2] is 0 and for bits[1:0] is b11.


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