6.4.7. Preload instruction behavior

The Cortex-A15 MPCore processor supports both the PLD and PLDW prefetch hint instructions. For Normal Write-Back Cacheable memory page, the preload instructions cause the line to be allocated to the L1 data cache of the executing core. The PLD instruction brings the line into the cache in Exclusive or Shared state and the PLDW instruction brings the line into the cache in Exclusive state. The preload instruction cache, PLDI, is treated as a NOP. PLD and PLDW instructions are performance hints instructions only and might be dropped in some cases.

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