4.3.29. Coprocessor Access Control Register

The CPACR characteristics are:

Purpose

Controls access to coprocessors CP0 to CP13. It also enables software to check for the presence of coprocessors CP0 to CP13.

Usage constraints

The CPACR:

  • Is a read/write register.

  • Is Common to the Secure and Non-secure states.

  • Is only accessible from PL1 or higher.

  • Has no effect on instructions executed in Hyp mode.

Configurations

This is a configurable access register. See the ARM Architecture Reference Manual for more information. Bits in the NSACR, see Non-Secure Access Control Register, control Non-secure access to the CPACR fields.

Attributes

See the register summary in Table 4.3.

Figure 4.25 shows the CPACR bit assignments.

Figure 4.25. CPACR bit assignments

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Table 4.54 shows the CPACR bit assignments.

Table 4.54. CPACR bit assignments

BitsNameFunction
[31]ASEDIS

Disable Advanced SIMD Extension functionality:

0

All Advanced SIMD and VFP instructions execute normally.

1

All Advanced SIMD instructions that are not VFP instructions are undefined.

If VFP is implemented and NEON is not implemented, this bit is RAO/WI.

If VFP and NEON are not implemented, this bit is UNK/SBZP.

[30]-

Reserved, RAZ/WI.

[29:28]-

Reserved, UNK/SBZP.

[27:24]-

Reserved, RAZ/WI.

[23:22]cp11

Defines the access rights for coprocessor 11:

b00

Access denied. Any attempt to access the coprocessor generates an Undefined Instruction exception. This is the reset value.

b01

Access at PL1 or higher only. Any attempt to access the coprocessor from software executing at PL0 generates an Undefined Instruction exception.

b10

Reserved. The effect of this value is unpredictable.

b11

Full access. The meaning of full access is defined by the appropriate coprocessor.

If VFP and NEON are not implemented, this bit is RAZ/WI.

[21:20]cp10

Defines the access rights for coprocessor 10:

b00

Access denied. Any attempt to access the coprocessor generates an Undefined Instruction exception. This is the reset value.

b01

Access at PL1 or higher only. Any attempt to access the coprocessor from software executing at PL0 generates an Undefined Instruction exception.

b10

Reserved. The effect of this value is unpredictable.

b11

Full access. The meaning of full access is defined by the appropriate coprocessor.

If VFP and NEON are not implemented, this bit is RAZ/WI.

[19:0]-

Reserved, RAZ/WI.


Note

If the values of the cp11 and cp10 fields are not the same, the behavior is unpredictable.

To access the CPACR, read or write the CP15 register with:

MRC p15, 0, <Rt>, c1, c0, 2; Read Coprocessor Access Control Register
MCR p15, 0, <Rt>, c1, c0, 2; Write Coprocessor Access Control Register
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