A.9.1. AXI master interface signals

The following sections describe the AXI master interface signals:

Clock and configuration signals

Table A.8 shows the clock and configuration signals for the AXI master interface.

Table A.8. Clock and configuration signals

SignalTypeDescription
ACLKENMInput

AXI master bus clock enable. See Clocking and resets for more information.

ACINACTMInput

Snoop interface is inactive and no longer accepting requests.

A64n128MInput

Selects 64-bit or 128-bit AXI bus width:

0

128-bit bus width.

1

64-bit bus width.

BROADCASTCACHEMAINTInput

Enable broadcasting of cache maintenance operations to downstream caches:

0

Cache maintenance operations are not broadcasted to downstream caches.

1

Cache maintenance operations are broadcasted to downstream caches.

This signal is only sampled during reset of the processor. See ACE configurations for more information.

BROADCASTINNERInput

Enable broadcasting of inner shareable transactions:

0

Inner shareable transactions are not broadcasted externally.

1

Inner shareable transactions are broadcasted externally.

If BROADCASTINNER is tied HIGH, you must also tie BROADCASTOUTER HIGH.

This signal is only sampled during reset of the processor. See ACE configurations for more information.

BROADCASTOUTERInput

Enable broadcasting of outer shareable transactions:

0

Outer shareable transactions are not broadcasted externally.

1

Outer shareable transactions are broadcasted externally.

This signal is only sampled during reset of the processor. See ACE configurations for more information.

SYSBARDISABLEInput

Disable broadcasting of barriers onto system bus:

0

Barriers are broadcasted onto system bus, this requires an AMBA 4 interconnect.

1

Barriers are not broadcasted onto the system bus. This is compatible with an AXI3 interconnect.

If SYSBARDISABLE is tied HIGH, you must tie the following signals LOW for full AXI3 compatibility:

  • BROADCASTCACHEMAINT.

  • BROADCASTINNER.

  • BROADCASTOUTER.

This signal is only sampled during reset of the processor. See ACE configurations for more information.


Asynchronous error signals

Table A.9 shows the asynchronous error signals.

Table A.9. Asynchronous error signals

SignalTypeDescription
nAXIERRIRQOutputError indicator for AXI write transactions with a BRESP error condition. Writing 0 to bit[29] of the L2ECTLR clears the error indicator, see L2 Extended Control Register for more information.
nINTERRIRQOutput

Error indicator for:

  • L2 RAM double-bit ECC error.

  • Illegal writes to the GIC memory-map region, see GIC configuration.

Writing 0 to bit[30] of the L2ECTLR clears the error indicator, see L2 Extended Control Register for more information.


Write address channel signals

Table A.10 shows the write address channel signals for the AXI master interface.

Table A.10. Write address channel signals

SignalTypeDescription
AWADDRM[39:0]OutputAddress
AWBARM[1:0]OutputBarrier type
AWBURSTM[1:0]Output

Burst type

AWCACHEM[3:0]Output

Cache type

AWDOMAINM[1:0]OutputDomain type
AWIDM[5:0]Output

Request ID

AWLENM[7:0]Output

Burst length

AWLOCKMOutput

Lock type

AWPROTM[2:0]Output

Protection type

AWREADYMInput

Address ready

AWSIZEM[2:0]Output

Burst size

AWSNOOPM[2:0]Output

Snoop request type

AWUSERM[1:0]Output

User signals:

b00

SharedClean

b01

UniqueClean

b10

SharedDirty

b11

UniqueDirty

AWVALIDMOutput

Address valid


Write data channel signals

Table A.11 shows the write data signals for the AXI master interface.

Table A.11. Write data channel signals

SignalTypeDescription
WDATAM[127:0]OutputWrite data
WIDM[5:0]OutputWrite ID
WLASTMOutputWrite last
WREADYMInputWrite ready
WSTRBM[15:0]OutputWrite strobes
WVALIDMOutputWrite valid

Write response channel signals

Table A.12 shows the write response channel signals for the AXI master interface.

Table A.12. Write response channel signals

SignalTypeDescription
BIDM[5:0]InputResponse ID
BREADYMOutputResponse ready
BRESPM[1:0]InputWrite response
BVALIDMInputResponse valid

Read address channel signals

Table A.13 shows the read address channel signals for the AXI master interface.

Table A.13. Read address channel signals

SignalTypeDescription
ARADDRM[39:0]Output

Address

ARBARM[1:0]OutputBarrier type
ARBURSTM[1:0]Output

Burst type

ARCACHEM[3:0]Output

Cache type

ARDOMAINM[1:0]OutputDomain type
ARIDM[5:0]Output

Request ID

ARLENM[7:0]Output

Burst length

ARLOCKMOutput

Lock type

ARPROTM[2:0]Output

Protection type

ARREADYMInput

Address ready

ARSIZEM[2:0]Output

Burst size

ARSNOOPM[3:0]Output

Snoop request type

ARVALIDMOutput

Address valid


Read data channel signals

Table A.14 shows the read data channel signals for the AXI master interface.

Table A.14. Read data channel signals

SignalTypeDescription
RDATAM[127:0]Input

Read data

RIDM[5:0]Input

Read ID

RLASTMInput

Read last

RREADYMOutput

Read ready

RRESPM[3:0]Input

Read response

RVALIDMInput

Read valid


Snoop address channel signals

Table A.15 shows the snoop address channel signals for the AXI master interface.

Table A.15. Snoop address channel signals

SignalTypeDescription
ACADDRM[39:0]Input

Address

ACPROTM[2:0]Input

Protection type

ACREADYMOutput

Address ready

ACSNOOPM[3:0]Input

Transaction type

ACVALIDMInput

Address valid


Snoop data channel signals

Table A.16 shows the snoop data channel signals for the AXI master interface.

Table A.16. Snoop data channel signals

SignalTypeDescription
CDDATAM[127:0]Output

Snoop data

CDLASTMOutput

Snoop last

CDREADYMInput

Snoop ready

CDVALIDMOutput

Snoop valid


Snoop response channel signals

Table A.17 shows the snoop response channel signals for the AXI master interface.

Table A.17. Snoop response channel signals

SignalTypeDescription
CRREADYMInput

Response ready

CRRESPM[4:0]Output

Snoop response

CRVALIDMOutput

Response valid


Read/write acknowledge signals

Table A.18 shows the read/write acknowledge signals for the AXI master interface.

Table A.18. Read/write acknowledge signals

SignalTypeDescription
RACKMOutput

Read acknowledge

WACKMOutput

Write acknowledge


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