7.7.8. ACE configuration signals

The Cortex-A15 MPCore processor implements the following ACE configuration signals:

Table 7.5 shows the permitted combinations of these signals and the supported configurations in the Cortex-A15 MPCore processor.

Table 7.5. Supported ACE configurations

SignalFeature    
 AXI3 modeACE non-coherent, no L3 cacheACE non-coherent, with L3 cacheACE outer coherentACE inner coherent
BROADCASTINNER00001
BROADCASTOUTER00011
BROADCASTCACHEMAINTENANCE00111
SYSBARDISABLE10000

Note

If the BROADCASTINNER and BROADCASTOUTER signals are deasserted, this implies that the Cortex-A15 MPCore processor is in a non-coherent system with no coherent masters on the ACE interconnect and no transactions can appear on the snoop AC channel.

Table 7.6 shows the key features in each of the supported ACE configurations.

Table 7.6. Supported features in the ACE configurations

FeaturesConfiguration    
 AXI3 modeACE non-coherent, no L3 cacheACE non-coherent, with L3 cacheACE outer coherentACE inner coherent
AXI3 complianceYNNNN
ACE complianceNYYYY
Barriers on AR channelNYYYY
Caches on AR channelNNYYY
Snoops on AC channelNNNYY
Coherent requests on AR or AW channelNNNYY
DVM requests on AR channelNNNNY

Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G
Non-ConfidentialID080412