10.4.9. Debug ROM Address Register

The DBGDRAR characteristics are:

Purpose

Defines the base physical address of a memory-mapped debug component, usually a ROM Table that locates and describes the memory-mapped debug components in the system.

Usage constraints

This register is only visible in the CP14 interface, and therefore does not have a memory offset.

Configurations

The DBGDRAR is:

  • a 64-bit register when accessed by the MRRC instruction

  • a 32-bit register when accessed by the MRC instruction.

Attributes

See the register summary in Table 10.1.

Figure 10.10 shows the DBGDRAR bit assignments as a 32-bit register.

Figure 10.10. DBGDRAR 32-bit register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Figure 10.11 shows the DBGDRAR bit assignments as a 64-bit register.

Figure 10.11. DBGDRAR 64-bit register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 10.11 shows the DBGDRAR bit assignments.

Table 10.11. DBGDRAR bit assignments

BitsNameFunction
[63:40]-

Reserved.

[39:32]ROMADDR[39:32]

Bits[39:32] of the debug component physical address. Bits[11:0] of the address are zero.

If DBGDRAR.Valid is zero, the value of this field is unknown.

[31:12]ROMADDR[31:12]

Bits[31:12] of the debug component physical address. Bits[11:0] of the address are zero.

If DBGDRAR.Valid is zero, the value of this field is unknown.

[11:2]-

Reserved.

[1:0]Valid

Valid bits. This field indicates whether the address is valid:

b00

Address is not valid.

b11

Address is valid.

Note

ROMADDRV must be set to 1 if ROMADDR[39:12] is set to a valid value.


Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G
Non-ConfidentialID080412