10.4.16. Integration Input Status Register

The DBGITISR characteristics are:

Purpose

Enables the values of signal inputs to be read when bit[0] of the Integration Mode Control Register is set.

Usage constraints

DBGITISR is not accessible on the extended CP14 interface.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 10.1.

Figure 10.19 shows the DBGITISR bit assignments.

Figure 10.19. DBGITISR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 10.18 shows the DBGITISR bit assignments.

Table 10.18. DBGITISR bit assignments

BitsNameFunction
[31:4]-Reserved, RAZ.
[3]DBGSWENABLEThis field reads the state of the DBGSWENABLE input.
[2]CTI DBGRESTART

CTI debug restart bit. This field reads the state of the debug restart input coming from the CTI into the debug unit.

[1]CTI EDBGRQ

CTI debug request bit. This field reads the state of the debug request input coming from the CTI into the debug unit.

[0]EDBGRQ

This field reads the state of the EDBGRQ input.


Copyright © 2011-2012 ARM. All rights reserved.ARM DDI 0438G
Non-ConfidentialID080412