10.4.4. Debug External Auxiliary Control Register

The DBGEACR characteristics are:

Purpose

Provides implementation-defined configuration and control options.

Usage constraints

The DBGEACR is not accessible from the CP14 interface.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 10.1.

Figure 10.5 shows the DBGEACR bit assignments.

Figure 10.5. DBGEACR bit assignments

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Table 10.5 shows the DBGEACR bit assignments.

Table 10.5. DBGEACR bit assignments

BitsNameFunction
[31:4]-

Reserved, RAZ/WI.

[3]Core debug reset status

Read-only status bit that reflects the current reset state of the debug logic in the processor power domain:

0

Debug logic in processor power domain is not in reset state.

1

Debug logic in processor power domain is currently in reset state.

[2]Debug extend core reset request

Debug core reset request extend bit. If debug is enabled and this bit is:

0

DBGRSTREQ is asserted for 16 cycles when 1'b1 is written to bit[1] of the Device Powerdown and Reset Control Register. See Device Powerdown and Reset Control Register. This is the reset value.

1

DBGRSTREQ is asserted for 64 cycles when 1'b1 is written to bit[1] of the Device Powerdown and Reset Control Register.

[1]Debug powerdown override

Debug powerdown control bit. If debug is enabled and this bit is:

0

Error response is generated for APB accesses to the core domain debug registers when the core is powered down or double lock is set. This is the reset value.

1

APB accesses to the core domain debug registers proceed normally when the core is powered down or double lock is set.

[0]Debug clock stop control

Debug clock control bit. If debug is enabled and this bit is:

0

Does not prevent the clock generator from stopping the processor clock. This is the reset value.

1

Prevents the clock generator from stopping the processor clock.


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