10.4.2. Program Counter Sampling Register

The DBGPCSR characteristics are:


Enables a debugger to sample the Program Counter (PC).

Usage constraints

ARM deprecates reading a PC sample through register 33 when the DBGPCSR is also implemented as register 40. DBGPCSR is not visible in the CP14 interface.


DBGPCSR is implemented as both debug register 33 and 40.


See the register summary in Table 10.1.

Figure 10.3 shows the DBGPCSR bit assignments.

Figure 10.3. DBGPCSR bit assignments

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Table 10.3 shows the DBGPCSR bit assignments.

Table 10.3. DBGPCSR bit assignments


Program Counter sample value. The sampled value of bits[31:1] of the PC. The sampled value is either the virtual address of an instruction, or the virtual address of an instruction address plus an offset that depends on the processor instruction set state.

DBGDEVID1.PCSROffset indicates whether an offset is applied to the sampled addresses. For the Cortex-A15 MPCore processor, an offset is applied.


This bit indicates whether the sampled address is an ARM instruction, or a Thumb or ThumbEEinstruction:


If DBGPCSR[1] is 0, the sampled address is an ARM instruction.


The sampled address is a Thumb or ThumbEE instruction.

If T is 0 then DBGPCSR[1] is 0, ((DBGPCSR[31:2] << 2) - 8) is the address of the sampled ARM instruction.

If T is 1, ((DBGPCSR[31:1] << 1) - 4) is the address of the sampled Thumb or ThumbEE instruction.

See the ARM Architecture Reference Manual for more information.

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