Table 10.1 shows
the 32-bit or 64-bit wide CP14 interface registers, accessed by
the MCR
, MRC
, MCCR
, or MRRC
instructions
in the order of CRn, Op1, CRm, Op2.
Table 10.1. CP14 debug register summary
Register number | Offset | CRn | Op1 | CRm | Op2 | Name | Type | Description |
---|---|---|---|---|---|---|---|---|
0 | 0x000 | c0 | 0 | c0 | 0 | DBGDIDR | RO | Debug ID Register |
1-5 | 0x004 -0x014 | - | - | - | - | - | - | Reserved |
6 | 0x018 | c0 | 0 | c6 | 0 | DBGWFAR | RW | Watchpoint Fault Address Register, UNK/SBZ |
7 | 0x01C | c0 | 0 | c7 | 0 | DBGVCR | RW | Vector Catch Register, see the ARM Architecture Reference Manual |
8 | 0x020 | - | - | - | - | - | - | Reserved |
9 | 0x024 | - | - | - | - | DBGECR | RW | Event Catch Register, see the ARM Architecture Reference Manual |
10 | 0x028 | c0 | 0 | c10 | 0 | - | - | Not implemented |
11 | 0x02C | c0 | 0 | c11 | 0 | - | - | Not implemented |
12-31 | 0x030-0x07C | - | - | - | - | - | - | Reserved |
32 | 0x080 | c0 | 0 | c0 | 2 | DBGDTRRX external view | RW | Host to Target Data Transfer, see the ARM Architecture Reference Manual |
33 | 0x084 | - | - | - | - | DBGITR | WO | Instruction Transfer Register, see the ARM Architecture Reference Manual |
DBGPCSR | RO | Program Counter Sampling Register | ||||||
34 | 0x088 | c0 | 0 | c2 | 2 | DBGDSCR external view | RW | Debug Status and Control Register, see the ARM Architecture Reference Manual |
35 | 0x08C | c0 | 0 | c3 | 2 | DBGDTRTX external view | RW | Target to Host Transfer, see the ARM Architecture Reference Manual |
36 | 0x090 | - | - | - | - | DBGDRCR | WO | Debug Run Control Register |
37 | 0x094 | - | - | - | - | DBGEACR | RW | Debug External Auxiliary Control Register |
38-39 | 0x098-0x09C | - | - | - | - | - | - | Reserved |
40 | 0x0A0 | - | - | - | - | DBGPCSR | RO | Program Counter Sampling Register |
41 | 0x0A4 | - | - | - | - | DBGCIDSR | RO | Context ID Sampling Register, see the ARM Architecture Reference Manual |
42 | 0x0A8 | - | - | - | - | DBGVIDSR | RO | Virtualization ID Sampling Register, see the ARM Architecture Reference Manual |
43-63 | 0x0AC-0x0FC | - | - | - | - | - | - | Reserved |
64-69 | 0x100-0x114 | c0 | 0 | c0-c5 | 4 | DBGBVRn | RW | Breakpoint Value Registers |
70-79 | 0x118-0x13C | - | - | - | - | - | - | Reserved |
80-85 | 0x140-0x154 | c0 | 0 | c0-c5 | 5 | DBGBCRn | RW | Breakpoint Control Registers |
86-95 | 0x158-0x17C | - | - | - | - | - | - | Reserved |
96-99 | 0x180-0x18C | c0 | 0 | c0-c3 | 6 | DBGWVRn | RW | Watchpoint Value Registers |
100-111 | 0x190-0x1BC | - | - | - | - | - | - | Reserved |
112-115 | 0x1C0-0x1CC | c0 | 0 | c0-c3 | 7 | DBGWCRn | RW | Watchpoint Control Registers |
116-147 | 0x1D0-0x24C | - | - | - | - | - | - | Reserved |
148-149 | 0x250-0x254 | c1 | 0 | c4-c5 | 1 | DBGBXVRn | RW | Breakpoint Extended Value Registers |
150-191 | 0x258-0x2FC | - | - | - | - | - | - | Reserved |
192 | 0x300 | c1 | 0 | c0 | 4 | DBGOSLAR | WO | OS Lock Access Register |
193 | 0x304 | c1 | 0 | c1 | 4 | DBGOSLSR | RO | OS Lock Status Register |
194 | 0x308 | - | - | - | - | - | - | Not implemented |
195 | 0x30C | - | - | - | - | - | - | Reserved |
196 | 0x310 | c1 | 0 | c4 | 4 | DBGPRCR | RW | Device Powerdown and Reset Control Register |
197 | 0x314 | - | - | - | - | DBGPRSR | RO | Device Powerdown and Reset Status Register, see the ARM Architecture Reference Manual |
198-831 | 0x318-0xCFC | - | - | - | - | - | - | Reserved |
832-895 | 0xD00-0xDFC | - | - | - | - | Processor ID registers | RO | Processor ID registers, see the ARM Architecture Reference Manual |
896-957 | 0xE00-0xEF4 | - | - | - | - | - | - | Reserved |
958 | 0xEF8 | - | - | - | - | DBGITOCTRL | WO | Integration Output Control Register |
959 | 0xEFC | - | - | - | - | DBGITISR | RO | Integration Input Status Register |
960 | 0xF00 | - | - | - | - | DBGITCTRL | RW | Integration Mode Control Register |
961-999 | 0xF04-0xF9C | - | - | - | - | - | - | Reserved |
1000 | 0xFA0 | c7 | 0 | c8 | 6 | DBGCLAIMSET | RW | Claim Tag Set Register |
1001 | 0xFA4 | c7 | 0 | c9 | 6 | DBGCLAIMCLR | RW | Claim Tag Clear Register |
1002-1003 | 0xFA8-0xFAC | - | - | - | - | - | - | Reserved |
1004 | 0xFB0 | - | - | - | - | DBGLAR | WO | Lock Access Register, see the ARM Architecture Reference Manual |
1005 | 0xFB4 | - | - | - | - | DBGLSR | RO | Lock Status Register, see the ARM Architecture Reference Manual |
1006 | 0xFB8 | c7 | 0 | c14 | 6 | DBGAUTHSTATUS | RO | Authentication Status Register, see the ARM Architecture Reference Manual |
1007 | 0xFBC | - | - | - | - | - | - | Reserved |
1008 | 0xFC0 | c7 | 0 | c0 | 7 | DBGDEVID2 | RO | UNK |
1009 | 0xFC4 | c7 | 0 | c1 | 7 | DBGDEVID1 | RO | Debug Device ID Register 1 |
1010 | 0xFC8 | c7 | 0 | c2 | 7 | DBGDEVID | RO | Debug Device ID Register |
1011 | 0xFCC | - | - | - | - | DBGDEVTYPE | RO | Device Type Register, see the ARM Architecture Reference Manual |
1012 | 0xFD0 | - | - | - | - | DBGPID4 | RO | Peripheral Identification Registers |
1013-1015 | 0xFD4-0xFDC | - | - | - | - | DBGPID5-7 | - | Reserved |
1016 | 0xFE0 | - | - | - | - | DBGPID0 | RO | Peripheral Identification Registers |
1017 | 0xFE4 | - | - | - | - | DBGPID1 | RO | |
1018 | 0xFE8 | - | - | - | - | DBGPID2 | RO | |
1019 | 0xFEC | - | - | - | - | DBGPID3 | RO | |
1020 | 0xFF0 | - | - | - | - | DBGCID0 | RO | Component Identification Registers |
1021 | 0xFF4 | - | - | - | - | DBGCID1 | RO | |
1022 | 0xFF8 | - | - | - | - | DBGCID2 | RO | |
1023 | 0xFFC | - | - | - | - | DBGCID3 | RO | |
- | - | c0 | 0 | c1 | 0 | DBGDSCR internal view | RO | Debug Status and Control Register, see the ARM Architecture Reference Manual |
- | - | c0 | 0 | c5 | 0 | DBGDTRRX internal view | WO | Host to Target Data Transfer, see the ARM Architecture Reference Manual |
DBGDTRTX internal view | RO | Target to Host Transfer, see the ARM Architecture Reference Manual | ||||||
- | -
| c1 | 0 | c0 | 0 | DBGDRAR (MRC) | RO | Debug ROM Address Register |
- | - | c1 | 0 | - | - | DBGDRAR (MRRC) | RO | Debug ROM Address Register |
- | - | c1 | 0 | c3 | 4 | DBGOSDLR | RW | OS Double Lock Register, see the ARM Architecture Reference Manual |
- | -
| c2 | 0 | c0 | 0 | DBGDSAR (MRC) | RO | Debug Self Address Offset Register |
- | - | c2 | 0 | - | - | DBGDSAR (MRRC) | RO | Debug Self Address Offset Register |