8.3.2. Distributor register descriptions

This section only describes registers whose implementation is specific to the Cortex-A15 MPCore processor. All other registers are described in the ARM Generic Interrupt Controller Architecture Specification. Table 8.3 provides cross references to individual registers.

Interrupt Controller Type Register

The GICD_TYPER characteristics are:

Purpose

Provides information about the configuration of the GIC. It indicates:

  • Whether the GIC implements the Security Extensions.

  • The maximum number of interrupt IDs that the GIC supports.

  • The maximum number of processor interfaces implemented.

  • If the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs).

Usage constraints

There are no usage constraints.

Configurations

Available if the GIC is implemented.

Attributes

See the register summary in Table 8.3.

Figure 8.1 shows the GICD_TYPER bit assignments.

Figure 8.1. GICD_TYPER bit assignments

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Table 8.4 shows the GICD_TYPER bit assignments.

Table 8.4. GICD_TYPER bit assignments

Bits Name Function
[31:16] - Reserved, RAZ.
[15:11] LSPI

Returns the number of Lockable Shared Peripheral Interrupts (LSPIs) that the GIC contains:

b11111

31 LSPIs. These are the interrupts of IDs 32-62.

When CFGSDISABLE is asserted, the GIC prevents writes to any register locations that control the operating state of an LSPI.

[10] SecurityExtn Indicates whether the GIC implements the Security Extensions. This bit always returns a value of 1, indicating that the Security Extensions are implemented.
[9:8] - Reserved, RAZ.
[7:5]CPUNumber

Indicates the number of implemented processor interfaces:

b000

The Cortex-A15 MPCore configuration contains one processor.

b001

The Cortex-A15 MPCore configuration contains two processors.

b010

The Cortex-A15 MPCore configuration contains three processors.

b011

The Cortex-A15 MPCore configuration contains four processors.

All other values are reserved for future expansions.

[4:0] ITLinesNumber

Indicates the number of interrupts that the GIC supports:

b00000

Up to 32 interrupts[a], no external interrupt lines.

b00001

Up to 64 interrupts, 32 external interrupt lines.

b00010

Up to 96 interrupts, 64 external interrupt lines.

b00011

Up to 128 interrupts, 96 external interrupt lines.

b00100

Up to 160 interrupts, 128 external interrupt lines.

b00101

Up to 192 interrupts, 160 external interrupt lines.

b00110

Up to 224 interrupts, 192 external interrupt lines.

b00111

Up to 256 interrupts, 224 external interrupt lines.

All other values are reserved for future expansions.

[a] The Distributor always uses interrupts of IDs 0 to 31 to control any SGIs and PPIs that the GIC might contain.


Distributor Implementer Identification Register

The GICD_IIDR characteristics are:

Purpose

Provides information about the implementer and revision of the Distributor.

Usage constraints

There are no usage constraints.

Configurations

Available if the GIC is implemented.

Attributes

See the register summary in Table 8.3.

Figure 8.2 shows the GICD_IIDR bit assignments.

Figure 8.2. GICD_IIDR bit assignments

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Table 8.5 shows the GICD_IIDR bit assignments.

Table 8.5. GICD_IIDR bit assignments

Bits Name Description
[31:24] ProductID

Indicates the product ID of the GIC:

0x00

Product ID.

[23:20] - Reserved, RAZ
[19:16] Variant

Indicates the major revision number of the GIC:

0x0

Variant number.

[15:12] Revision

Indicates the minor revision number of the GIC:

0x0

Revision number.

[11:0] Implementer

Indicates the implementer:

0x43B

ARM implementation.


Interrupt Configuration Register

The GICD_ICFGR provides a 2-bit field that describes the configuration for each interrupt that the GIC supports.

The options for each bit-pair depend on the interrupt type as follows:

SGI

The bits are read-only and a bit-pair always reads as b10 because SGIs are edge-triggered.

PPI

The bits are read-only and a bit-pair always reads as b01. Table 8.6 shows that the PPIs are implemented as level-sensitive.

Table 8.6. PPI implementation

InterruptNameLevel-sensitive
PPI6Virtual Maintenance interruptactive-HIGH
PPI5Hypervisor timer eventactive-LOW
PPI4Virtual timer eventactive-LOW
PPI3Legacy nIRQ pinactive-LOW
PPI2Non-secure physical timer eventactive-LOW
PPI1Secure physical timer eventactive-LOW
PPI0Legacy nFIQ pinactive-LOW

SPI

The Least Significant Bit (LSB) of the bit-pair is read-only and is always 1. You can program the Most Significant Bit (MSB) of the bit-pair to alter the triggering sensitivity as follows:

b01

Interrupt is active-HIGH level-sensitive.

b11

Interrupt is rising edge-sensitive.

Private Peripheral Interrupt Status Register

The GICD_PPISR characteristics are:

Purpose

Enables a Cortex-A15 MPCore processor to access the status of the PPI inputs on the Distributor.

Usage constraints

A processor can only read the status of its own PPI and therefore cannot read the status of the PPI for other processors.

Configurations

Available if the GIC is implemented.

Attributes

See the register summary in Table 8.3.

Figure 8.3 shows the GICD_PPISR bit assignments.

Figure 8.3. GICD_PPISR bit assignments

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Table 8.7 shows the GICD_PPISR bit assignments.

Table 8.7. GICD_PPISR bit assignments

Bits Name Description
[31:16] - Reserved, RAZ
[15:9] PPI status

Returns the status of the PPI[6:0] inputs on the Distributor:

PPI6

Virtual Maintenance Interrupt.

PPI5

Hypervisor timer event.

PPI4

Virtual timer event.

PPI3

nIRQ.

PPI2

Non-secure physical timer event.

PPI1

Secure physical timer event.

PPI0

nFIQ.

PPI0-5

Active-LOW level-sensitive.

PPI6

Active-HIGH level-sensitive.

Note

These bits return the actual status of the PPI[6:0] signals. The GICD_ISPENDRn and GICD_ICPENDRn can also provide the PPI[6:0] status but because you can write to these registers, they might not contain the true status of the PPI[6:0] signals.

[8:0]-Reserved, RAZ

Shared Peripheral Interrupt Status Registers

The GICD_SPISR characteristics are:

Purpose

Enables a Cortex-A15 MPCore processor to access the status of the IRQS[223:0] inputs on the Distributor.

Usage constraints

There are no usage constraints.

Configurations

Available if the GIC is implemented.

Attributes

See the register summary in Table 8.3.

Figure 8.4 shows the GICD_SPISR bit assignments.

Figure 8.4. GICD_SPISR bit assignments

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Table 8.8 shows the GICD_SPISR bit assignments.

Table 8.8. GICD_SPISR bit assignments

Bits Name Function
[31:0] IRQS[N+31:N]

Returns the status of the IRQS[223:0] inputs on the Distributor. For each bit:

0

IRQS is LOW.

1

IRQS is HIGH.

Note

  • The IRQS that a bit refers to depends on its bit position and the base address offset of the GICD_SPISR.

  • These bits return the actual status of the IRQS signals. The GICD_ISPENDRn and GICD_ICPENDRn can also provide the IRQS status but because you can write to these registers, they might not contain the actual status of the IRQS signals.


Figure 8.5 shows the address map that the Distributor provides for the SPIs.

Figure 8.5. GICD_SPISR address map

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The Distributor provides up to seven registers to support 224 SPIs. If the GIC is configured to use fewer than 224 SPIs, it reduces the number of registers accordingly. For locations where interrupts are not implemented, the bit is RAZ/WI.

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