8.2.2. GIC memory-map

The GIC registers are memory-mapped, with a physical base address specified by PERIPHBASE[39:15]. This input must be tied to a constant value. The PERIPHBASE value is sampled during reset into the Configuration Base Address Register (CBAR) for each processor in the MPCore device. See Configuration Base Address Register.

The GIC registers are grouped into four contiguous 4KB or 8KB pages. The Distributor block reside in the 4KB page, while the CPU interface, virtual interface control, and virtual CPU interface blocks reside in the 8KB pages.

Memory regions used for these registers must be marked as Device or Strongly-ordered in the translation tables. Memory regions marked as Normal memory cannot access any of the GIC registers, but can access caches or external memory as required.

Access to these registers must be with the single load and store instructions. Load-multiple and load-double instructions result in a data abort exception to the requesting processor. Store-multiple and store-double instructions result in the assertion of nINTERRIRQ.

Most of the registers can only be accessed with a word-size request. Some registers can also be accessed with a byte-size request. Halfword and doubleword reads result in a data abort exception to the requesting processor. Halfword and doubleword writes result in the assertion of nINTERRIRQ.

The Accelerator Coherency Port (ACP) cannot access any of the GIC registers. The registers must be accessed through one of the processors. Any access from ACP to the GIC registers goes to external memory and no data abort exception is generated.

Table 8.1 lists the address offsets for the GIC blocks relative to the PERIPHBASE base address. Read access to reserved regions results in a data abort exception to the requesting processor. Write access to reserved regions results in the assertion of nINTERRIRQ.

Table 8.1. Cortex-A15 MPCore GIC memory map

Base offset from PERIPHBASE[39:15]Offset range from PERIPHBASE[39:15]GIC block
0x00000x0000 - 0x0FFFReserved
0x10000x1000 - 0x1FFFDistributor
0x20000x2000 - 0x3FFFCPU interface
0x40000x4000 - 0x4FFFVirtual interface control (common base address)
0x50000x5000 - 0x5FFFVirtual interface control (processor-specific base address)
0x60000x6000 - 0x7FFFVirtual CPU interface

Note

The GIC provides two ways to access the GIC virtual interface control registers:

  • A single common base address for the GIC virtual interface control registers. Each processor can access its own GIC virtual interface control registers through this base address. This base address is at offset 0x4000 relative to the PERIPHBASE address.

  • A different base address for each processor to access the GIC virtual interface control registers. Any processor can use these addresses to access its own GIC virtual interface control registers, or to access the GIC virtual interface control registers of any other processor in the MPCore device. The starting base address is at offset 0x5000 relative to the PERIPHBASE address, with address bits[10:9] as the CPU ID decode.

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