11.4.5. Peripheral Identification Registers

The Peripheral Identification Registers provide standard information required for all components that conform to the ARM PMUv2 architecture. They are a set of eight registers, listed in register number order in Table 11.5.

Table 11.5. Summary of the Peripheral Identification Registers

Peripheral ID40x040xFD0
Peripheral ID50x000xFD4
Peripheral ID60x000xFD8
Peripheral ID70x000xFDC
Peripheral ID00xAF0xFE0
Peripheral ID10xB90xFE4
Peripheral ID20x3B0xFE8
Peripheral ID30x000xFEC

Only bits[7:0] of each Peripheral ID Register are used, with bits[31:8] reserved. Together, the eight Peripheral ID Registers define a single 64-bit Peripheral ID.

The ARM Architecture Reference Manual describes these registers.

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