11.4.1. Performance Monitor Configuration Register

The PMCFGR characteristics are:

Purpose

Contains PMU-specific configuration data.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 11.1.

Figure 11.2 shows the PMCFGR bit assignments.

Figure 11.2. PMCFGR bit assignments

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Table 11.2 shows the PMCFGR bit assignments.

Table 11.2. PMCFGR bit assignments

BitsNameFunction
[31:20]-

Reserved.

[19]UEN

User mode enable register supported bit:

1

User mode enable register supported. PMUSERENR is a writable register.

[18:17]-

Reserved.

[16]EX

Export supported:

1

Export is supported. PMCR.X is writable.

[15]CCD

Cycle count divider implemented:

1

The cycle count divider implemented. PMCR.D is writable.

[14]CC

Cycle counter implemented:

1

Dedicated cycle counter is supported. PMCR.C is writable.

[13:8]Size

Counter size. This field is RO and reads as b011111:

b011111

32-bit counters.

[7:0]N

Number of event counters:

b00000110

Six counters.

Note

The cycle counter is not included in the value indicated by the N field.

The value of HDCR.HPMN has no effect on the value returned by this field.


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